Semiconductor Package Interconnect Structure for Dense POP Routing
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving high integration density and cost-effective packaging techniques for semiconductor devices, particularly in the context of Package-on-Package (POP) technology, where existing methods struggle to efficiently utilize smaller interconnect structures and core substrates to enhance component density and functionality.
Innovation Solution
The proposed solution involves forming multiple interconnect structures with integrated devices and passive components on smaller substrates, which are then attached to core substrates and encapsulated, allowing for improved yield and design flexibility through the use of smaller interconnect components and larger through vias for enhanced electrical routing and power handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional packaging methods are used, then manufacturing simplicity is maintained, but integration density and component density are insufficient
Solution Approach 1:
The packaging system is divided into separate modules: core substrates, interconnect structures, and passive component structures. Each module can be manufactured independently and then assembled, allowing for high integration density without proportionally increasing overall packaging complexity. The interconnect structures act as intermediate modules that bridge the core substrate and passive components.
Solution Approach 2:
The patent implements a hierarchical nesting structure where interconnect structures are attached to core substrates, and passive component structures are subsequently attached to the interconnect structures. This nested arrangement maximizes component density by utilizing vertical stacking and three-dimensional space efficiently, rather than simple planar placement.
2Quantity of substance
If smaller interconnect structures are used, then component density increases, but manufacturing precision requirements increase
Solution Approach 1:
Interconnect structures are manufactured and prepared in advance as separate modules before being attached to core substrates. This preliminary fabrication allows for precise control of interconnect dimensions and characteristics in a dedicated manufacturing process, rather than attempting to create precise features during final assembly. The pre-fabricated interconnect structures can be tested and validated before integration.
Solution Approach 2:
The patent employs different structure sizes and geometries optimized for specific functions: smaller interconnect structures where high density is required, and larger through vias where high-power applications demand enhanced electrical routing and power handling capabilities. This local optimization allows component density to increase in appropriate areas without uniformly increasing manufacturing precision requirements across the entire device.
3Productivity
If multiple interconnect structures are formed on smaller substrates, then units per wafer increases, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming multiple interconnect structures on a wafer, attaching the wafer to core substrates, and then attaching passive component structures to the interconnect structures. This segmentation allows high-volume parallel fabrication of interconnect structures to increase units per wafer, while the attachment steps can be performed with appropriate precision equipment without requiring the entire complex process to run at maximum speed simultaneously.
4Power
If larger through vias are used, then power handling capability improves, but area occupied increases
Solution Approach 1:
The patent uses larger through vias with enhanced dimensions specifically in regions where high-power applications require enhanced electrical routing and power handling capabilities, while maintaining smaller interconnect structures in areas where high density is the primary requirement. This localized optimization allows power handling capability to improve where needed without uniformly increasing the area occupied by all interconnect structures.
Data Source
AI summary
A method includes attaching interconnect structures to a carrier substrate, wherein each interconnect structure includes a redistribution structure; a first encapsulant on the redistribution structure; and a via extending through the encapsulant to physically and electrically connect to the redistribution structure; depositing a second encapsulant on the interconnect structures, wherein adjacent interconnect structures are laterally separated by the second encapsulant; after depositing the second encapsulant, attaching a first core substrate to the redistribution structure of at least one interconnect structure, wherein the core substrate is electrically connected to the redistribution structure; and attaching semiconductor devices to the interconnect structures, wherein the semiconductor devices are electrically connected to the vias of the interconnect structures.