Semiconductor Package Conductive Posts Insulation Body

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Solution Overview

Problem

Current semiconductor package technologies face challenges in achieving high-density, high-performance electrical connections with fine-pitch structures, particularly in three-dimensional (3D) packages, where existing methods like wire-bond and flip chips are limited by connection length and density.

Innovation Solution

A semiconductor device package is designed with a semiconductor substrate having conductive posts and an insulation body, where the conductive posts are separated by the insulation layer, allowing for improved electrical performance through precise pitch adjustment and insulation material usage, such as passivation materials or polymers, to enhance signal and ground path connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wire-bond or flip chip connections are used to create 3D packages, then electrical connections can be established, but the connection length is longer and the density is lower compared to TSV

Engineering Contradiction:
Improveconnection densityVSAvoidconnection length
Core Design Contradiction:
ProductivityVSLength of moving object

Solution Approach 1:

The patent transitions from planar surface connections (wire-bond, flip chip) to three-dimensional through-silicon via connections, utilizing the vertical dimension to pass through the substrate. This dimensional change enables shorter connection paths and higher density by exploiting the Z-axis space within the substrate thickness.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The insulation bodies are embedded within the semiconductor substrate, with conductive posts nested inside these insulation bodies. This nested structure allows multiple conductive elements to be packed closely together within the substrate volume, increasing connection density while maintaining electrical isolation.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Productivity

If conductive posts are placed closely together to achieve fine-pitch structure, then connection density increases, but mutual interference between adjacent posts increases

Engineering Contradiction:
Improvefine-pitch structure densityVSAvoidmutual interference
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

Insulation bodies made of low-dielectric constant materials are positioned between adjacent conductive posts to serve as electrical intermediaries. These insulation bodies reduce capacitive coupling and mutual interference between closely spaced conductive posts, enabling fine-pitch structures to function reliably.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the dielectric parameter (dielectric constant) of the insulation material to a low value, which reduces the electrical field interaction between adjacent conductive posts. This parameter change allows closer spacing of conductive posts without excessive mutual interference, achieving finer pitch structures.

Inventive Principle:
Principle #35Parameter changes

3Object-generated harmful factors

If insulation material is used to separate conductive posts, then mutual interference is reduced, but the structural complexity increases

Engineering Contradiction:
Improvemutual interferenceVSAvoidstructural complexity
Core Design Contradiction:
Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The insulation bodies are integrated directly into the substrate structure during manufacturing, merging the insulation function with the substrate itself. This integration approach reduces overall structural complexity compared to adding separate insulation layers, as the insulation and substrate become a unified structure.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10236208B2Semiconductor package structure and method of manufacturing the same
Publication Date: 2019.03.19 ADVANCED SEMICON ENG INC
  • US10236208B2 patent drawing
  • US10236208B2 patent drawing
  • US10236208B2 patent drawing

AI summary

The present disclosure relates to a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor substrate having a first surface and a second surface opposite the first surface. The semiconductor substrate has a space extending from the second surface to the first surface and an insulation body is disposed in the space. The semiconductor package structure includes conductive posts in the insulation body.