Semiconductor Package Power Line Layout for Reliable Chip-to-PCB Connection

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Solution Overview

Problem

Existing semiconductor packages face challenges in achieving improved electrical characteristics and reliability, particularly in the connection and wiring configurations between the semiconductor chip and the printed circuit board.

Innovation Solution

The semiconductor package incorporates a base substrate with power bumps and a semiconductor chip, featuring specific wiring configurations including first and second line wiring parts and connection wiring parts, with power pads and bumps arranged to enhance electrical connectivity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power lines are arranged in a conventional single-line configuration, then the device complexity is low, but the electrical characteristics and reliability are insufficient

Engineering Contradiction:
Improveelectrical characteristics and reliabilityVSAvoidwiring configuration complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The power line is divided into multiple line wiring parts (first line wiring part, second line wiring part, third line wiring part) that are spatially separated in the second direction. This segmentation allows each wiring part to be independently optimized and reduces interference between power lines, thereby improving electrical characteristics while maintaining manageable complexity through modular arrangement

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a conventional single-dimensional power line arrangement to a multi-dimensional configuration by spacing multiple line wiring parts apart in the second direction (transverse direction). This dimensional expansion enables better electrical isolation and improved current distribution without significantly increasing overall device complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple line wiring parts are spaced apart in the second direction, then electrical characteristics improve, but the area occupied by the power line increases

Engineering Contradiction:
Improveelectrical characteristicsVSAvoidarea occupied by power line
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The connection wiring parts are strategically positioned at specific locations where line wiring parts need to be coupled. This localized wiring approach concentrates the necessary connections at critical points while maintaining spacing between power-carrying segments, thereby improving electrical characteristics without proportionally increasing the total area occupied by the power line structure

Inventive Principle:
Principle #3Local quality

3Reliability

If connection wiring parts are used to couple line wiring parts, then electrical connectivity and reliability improve, but the manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidalignment precision of wiring parts
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Connection wiring parts serve as intermediary elements that couple the separated line wiring parts. These connection components provide a buffer zone for alignment tolerances and facilitate electrical connectivity between spaced-apart wiring segments, thereby maintaining high electrical connectivity and reliability while reducing the stringent alignment precision requirements that would otherwise be necessary

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260076230A1Semiconductor package with power line
Publication Date: 2026.03.12 SAMSUNG ELECTRONICS CO LTD
  • US20260076230A1 patent drawing
  • US20260076230A1 patent drawing
  • US20260076230A1 patent drawing

AI summary

A semiconductor package includes a base substrate, a plurality of power bumps on the base substrate, and a semiconductor chip on the plurality of power bumps. The base substrate includes a first power line in contact with the plurality of power bumps. The first power line includes a first line wiring part extending in a first direction, a second line wiring part extending in the first direction and spaced apart from the first line wiring part in a second direction intersecting the first direction, and a connection wiring part coupling the first line wiring part with the second line wiring part. The semiconductor chip includes a plurality of first power pads at least partially overlapping the first line wiring part, and a plurality of second power pads at least partially overlapping the second line wiring part.