Semiconductor Package Layout With Back-Side Power Delivery Separation

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Solution Overview

Problem

Existing semiconductor packages face challenges in signal integrity, power integrity, and thermal conduction due to the competition between signal and power delivery networks on the back-side of the chip, leading to potential degradation in performance.

Innovation Solution

A semiconductor package design that separates signal and power delivery networks by using a back-side power delivery network (BSPDN) with dedicated routing layers and through mold vias, allowing for decoupling of signals and power/ground, and incorporating a carrier with through vias for improved thermal conductivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If signal and power delivery networks share the back-side routing layers, then device complexity is reduced, but signal integrity and power integrity deteriorate

Engineering Contradiction:

Improverouting structure complexityVSAvoidsignal integrity

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The back-side routing layers are segmented into separate signal routing regions and power delivery regions. Signal lines and power/ground lines are routed in different layers and regions, preventing interference and maintaining both signal integrity and power integrity while managing complexity through organized separation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Through-mold vias (TMVs) serve as intermediary connection elements that vertically connect the back-side power delivery network with the front-side signal network. These TMVs are strategically positioned to provide dedicated power delivery paths without interfering with signal routing, acting as mediators between the separated power and signal domains.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Volume of moving object

If high density interconnects are used for signal routing and power delivery, then miniaturization is achieved, but thermal conduction and voltage drop issues worsen

Engineering Contradiction:

Improvepackage sizeVSAvoidthermal conduction

Core Design Contradiction:

Volume of moving objectVSTemperature

Solution Approach 1:

Power delivery is transitioned from the traditional planar front-side routing to the back-side three-dimensional space. The back-side power delivery network utilizes multiple routing layers and vertical TMVs to create a volumetric power distribution system, enabling efficient power delivery and thermal management in a compact footprint by exploiting the third dimension.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Different regions of the package are assigned different functional qualities: the back-side is dedicated to power delivery with high-density power lines and ground planes, while the front-side maintains signal routing. This local specialization allows each region to be optimized for its specific function, improving both thermal conduction in power regions and signal integrity in signal regions.

Inventive Principle:

Principle #3Local quality

3Reliability

If back-side power delivery network is implemented, then power integrity is improved, but manufacturing complexity increases

Engineering Contradiction:

Improvepower integrityVSAvoidfabrication process complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The back-side power delivery network structures, including routing layers and via holes, are prepared and formed during the semiconductor fabrication process before chip assembly. Through-mold vias are pre-formed in the mold compound, and power routing patterns are pre-established on the back-side, enabling subsequent chip placement and wire bonding without requiring complex post-assembly manufacturing steps.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances signal integrity by relaxing power integrity issues, optimizing power delivery, and increasing thermal performance through dedicated routing and improved thermal conductivity, enabling 3D stacking configurations.

Implementation Method 1

increasing thermal performance through dedicated routing and improved thermal conductivity

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

incorporating a carrier with through vias for improved thermal conductivity

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20260076225A1Semiconductor package and semiconductor package assembly

Publication Date: 2026.03.12 MEDIATEK INC

AI summary

A semiconductor package and a semiconductor package assembly are provided. The semiconductor package includes an interconnect structure, a chip, a redistribution layer (RDL), a molding compound, and through mold vias (TMVs). The chip is arranged on and coupled to the interconnect structure. The RDL is arranged on and coupled to the chip. The molding compound is arranged on the interconnect structure and encapsulates the chip and the RDL. The TMVs pass through the molding compound and are connected between the RDL and the interconnect structure. The chip includes a back-side connect structure, a transistor layer, a front-side connect structure and a carrier. The back-side connect structure is connected to the interconnect structure. The transistor layer is located on the back-side connect structure. The front-side connect structure is located on the transistor layer. The first carrier is located on and coupled to the interconnect structure.