Semiconductor Package Bottom Surface Protection Layer Design
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Solution Overview
Problem
As semiconductor packages become thinner and smaller, they are more susceptible to damage from external physical impacts or scratches, which existing technologies fail to adequately address.
Innovation Solution
A semiconductor package design that includes a protection layer covering the bottom surface of the semiconductor chip in specific regions, while leaving the connection bumps exposed, to prevent damage without interfering with their functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a protection layer covers the entire bottom surface of the semiconductor chip, then the chip is protected from physical impact and scratches, but the connection bumps cannot be properly formed or function
Solution Approach 1:
The protection layer is applied selectively to different regions of the semiconductor chip bottom surface. The edge region receives the protection layer for physical protection, while the center region remains exposed to allow connection bump formation and function. This local differentiation resolves the contradiction by providing protection only where it is needed without interfering with the connection bumps.
2Length of moving object
If the semiconductor package is made thinner and smaller, then the package meets miniaturization requirements, but the chip becomes more vulnerable to external physical impact and scratches
Solution Approach 1:
The bottom surface of the semiconductor chip is divided into two functional regions: an edge region that receives the protection layer for physical protection, and a center region that remains exposed for connection bump functionality. This segmentation allows the package to be miniaturized while protecting the vulnerable edges without compromising the connection bumps in the center region.
Data Source
AI summary
A semiconductor package includes a semiconductor chip that includes a first region and a second region spaced apart from the first region; a plurality of connection bumps disposed under the first region of the semiconductor chip; and a protection layer that covers a bottom surface of the semiconductor chip in the second region, wherein the protection layer does not cover the bottom surface of the semiconductor chip in the first region and is not disposed between the plurality of connection bumps. The semiconductor chip of the semiconductor package is protected by the protection layer.