Semiconductor Package Structure With Redistribution Circuit Layer
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Solution Overview
Problem
Conventional semiconductor packaging methods face challenges in reducing chip package thickness and size while maintaining electrical reliability, especially when stacking multiple chips, due to limitations in redistributing contacts and the use of molding compounds which can contaminate active surfaces and prevent vertical stacking.
Innovation Solution
A semiconductor package structure is developed using a first dielectric layer with through holes and a second dielectric layer with conductive vias, where the chip is embedded with a redistribution circuit layer extending onto the active surface and solder balls placed in the through holes, allowing for electrical connection and enabling three-dimensional stacking with improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If molding compound is used to package chip for increasing chip area, then chip area is increased, but molding compound extends onto active surface causing contamination and overflow defects
Solution Approach 1:
The patent changes the spatial arrangement by forming solder balls on the bottom surface of the molding compound at a different plane level than the active surface of the chip. This dimensional separation prevents molding compound overflow from contaminating the active surface while maintaining increased chip area, thereby resolving the contradiction between area expansion and manufacturing precision.
2Area of stationary object
If molding compound is used to package chip for increasing chip area, then chip area is increased, but active surface and solder balls are on same plane preventing vertical stacking
Solution Approach 1:
The patent utilizes vertical dimensionality by positioning solder balls on the bottom surface of the molding compound at a lower plane than the chip's active surface. This creates vertical clearance that enables multiple chips to be stacked in the Z-direction, transforming a two-dimensional layout constraint into a three-dimensional stacking capability while maintaining increased chip area.
3Area of moving object
If chip area is made smaller with semiconductor technology development, then integration density is improved, but interval between contacts becomes too small affecting electrical reliability
Solution Approach 1:
The patent relocates solder balls to the bottom surface of the molding compound, creating a vertical separation between the chip's active surface contacts and the external connection points. This dimensional transformation allows for larger spacing between contacts on the chip surface while maintaining small chip area, thereby preserving electrical reliability through improved signal integrity and reduced interference.
4Ease of manufacture
If redistribution circuit layer is located only on active surface and molding compound surface with same direction, then manufacturing is simplified, but multiple chips cannot be stacked
Solution Approach 1:
The patent extends the redistribution circuit layer to include connections on the bottom surface of the molding compound at a different vertical level. This creates a multi-planar redistribution architecture that maintains manufacturing simplicity through extended layer routing while enabling vertical stacking by providing connection points at multiple Z-heights, thus resolving the contradiction between ease of manufacture and stacking capability.
Data Source
AI summary
A manufacturing method of semiconductor package structure includes: providing a first dielectric layer having multiple through holes; providing a second dielectric layer having multiple conductive vias and a chip-containing opening; laminating the second dielectric layer onto the first dielectric layer; disposing a chip in the chip-containing opening and adhering a rear surface of the chip onto the first dielectric layer exposed by the chip-containing opening; forming a redistribution circuit layer on the second dielectric layer wherein a part of the redistribution circuit layer extends from the second dielectric layer onto an active surface of the chip and the conductive vias so that the chip electrically connects the conductive vias through the partial redistribution circuit layer; forming multiple solder balls on the first dielectric layer wherein the solder balls are in the through holes and electrically connect the chip through the conductive vias and the redistribution circuit layer.