Semiconductor Package Redistribution Layout for Lower Height Integration

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Solution Overview

Problem

The increasing demand for high-performance semiconductor devices with fine patterns and high integration requires thinner substrates, posing challenges in manufacturing semiconductor packages with fine widths or gaps, and existing technologies struggle to efficiently integrate semiconductor chips with advanced redistribution structures.

Innovation Solution

A semiconductor package design featuring an upper redistribution structure on the back surface of a semiconductor chip, with a lower redistribution structure, connecting members, an encapsulant, and upper bonding pads, allowing for vertical level differences and separate formation of redistribution structures to enhance integration and reduce vertical height.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the substrate is made thinner to accommodate fine patterns and high integration, then manufacturing precision and integration density improve, but structural stability and ease of manufacture deteriorate

Engineering Contradiction:
Improvefine pattern widthVSAvoidsubstrate thickness
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent transitions from planar redistribution to three-dimensional vertical stacking of redistribution structures. Multiple redistribution structures are arranged vertically at different heights, allowing fine patterns to be implemented while maintaining adequate substrate thickness for manufacturability. The connecting members extend vertically to interconnect these stacked structures, effectively utilizing the vertical dimension to resolve the contradiction between thin substrate requirements and manufacturing stability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If traditional planar redistribution structures are used, then ease of manufacture is maintained, but integration density and vertical space utilization deteriorate

Engineering Contradiction:
Improvemanufacturing processVSAvoidintegration density
Core Design Contradiction:
Ease of manufactureVSProductivity

Solution Approach 1:

The invention moves from two-dimensional planar redistribution to three-dimensional vertical stacking. Multiple redistribution structures are positioned at different vertical levels and interconnected via connecting members, dramatically increasing integration density while maintaining manufacturing feasibility through established vertical stacking processes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested redistribution structures where smaller redistribution structures are positioned within or between larger ones in the vertical stacking arrangement. This nested configuration maximizes space utilization and integration density while maintaining a compact overall structure that is manageable with current manufacturing capabilities.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Length of stationary object

If vertical height is reduced for compact packaging, then device size improves, but space for connecting members and structural integrity deteriorate

Engineering Contradiction:
Improvevertical heightVSAvoidconnecting member space
Core Design Contradiction:
Length of stationary objectVSReliability

Solution Approach 1:

The patent utilizes vertical stacking to arrange connecting members and redistribution structures in the vertical dimension rather than spreading them out horizontally. This three-dimensional arrangement achieves compact packaging with reduced overall footprint while maintaining adequate vertical spacing for connecting members, thereby preserving structural integrity and reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260068700A1Semiconductor package including redistribution structures
Publication Date: 2026.03.05 SAMSUNG ELECTRONICS CO LTD
  • US20260068700A1 patent drawing
  • US20260068700A1 patent drawing
  • US20260068700A1 patent drawing

AI summary

A semiconductor package includes a lower redistribution structure including a lower connection pad, a semiconductor chip on the lower redistribution structure, an upper redistribution structure on a back surface of the semiconductor chip and including a first connection region and a second connection region, a connecting member electrically connecting the lower connection pad and the first connection region, an encapsulant covering the semiconductor chip and surrounding a side surface of the upper redistribution structure, and an upper bonding pad on the upper redistribution structure and electrically connected to the second connection region. The second connection region is at a vertical level higher than a vertical level of the first connection region. The second connection region is coplanar with an upper surface of the encapsulant.