Semiconductor Package With Segmented Passivation Layers
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Solution Overview
Problem
Conventional semiconductor diode packaging technologies face challenges in achieving high breakdown voltage and low parasitic inductance, which limits the operating frequency and efficiency of power semiconductor diodes due to incompatible dielectric material thickness and high parasitic inductance issues.
Innovation Solution
A semiconductor device package structure is developed with multiple passivation layers of differing thickness, including a thin silicon nitride or oxide layer and a thicker polyimide or epoxy layer, along with metal interconnects, to provide high breakdown voltage and minimize parasitic inductance, while maintaining compatibility with power overlay packaging techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high dielectric material with increased thickness is used to provide high reverse breakdown voltage, then the breakdown voltage capability is improved, but the parasitic inductance increases and compatibility with POL packaging is reduced
Solution Approach 1:
The dielectric isolation structure is segmented into multiple layers: a first dielectric layer (30) providing high breakdown voltage and a second dielectric layer (32) providing mechanical support and additional isolation. This segmentation allows each layer to be optimized for its specific function, with the first layer focused on electrical isolation and the second on structural integrity, thereby reducing overall parasitic inductance while maintaining high breakdown voltage capability.
Solution Approach 2:
The patent employs composite dielectric structures combining different materials with complementary properties. The first dielectric layer uses high-k materials for superior electrical isolation, while the second dielectric layer uses materials optimized for mechanical strength and thermal management. This composite approach enables simultaneous optimization of electrical performance (high breakdown voltage) and electrical parasitics (low inductance).
2Strength
If conventional packaging technologies are used to provide mechanical protection and heat dissipation, then the structural integrity is improved, but the parasitic inductance increases and operating frequency is limited
Solution Approach 1:
The patent transitions from conventional two-dimensional planar packaging to a three-dimensional stacked architecture. Power devices are vertically stacked with integrated heat dissipation structures extending in the vertical dimension. This dimensional change reduces current loop areas and parasitic inductance while maintaining structural integrity through vertical load paths and enhanced thermal conduction in the vertical direction.
Solution Approach 2:
The packaging structure implements nested configurations where heat dissipation structures are integrated within the vertical stack of power devices. Thermal management components are nested between device layers, and interconnect structures are nested within the vertical architecture. This nesting reduces overall package height while minimizing current loop areas and parasitic inductance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure achieves a high breakdown voltage of up to 10 kV with reduced parasitic inductance, enabling efficient operation at improved frequencies and signal strength for power semiconductor diodes.
Implementation Method 1
Multiple passivation layers are formed about a semiconductor device, with the passivation layers having a thickness that provides a desired breakdown voltage for the semiconductor device package
Implementation Method 2
a plurality of metal interconnects electrically coupled to the plurality of metallic connection pads of the semiconductor device, with each of the plurality of metal interconnects extending through a respective via formed through the first and second passivation layers and the base dielectric laminate sheet to form a direct metallic connection with one of the plurality of metallic connection pads
Data Source
Figure 1
Figure 2~3
Figure 4A~4C
AI summary
A semiconductor device package 10 includes a semiconductor device 12 having connection pads formed 16 thereon, with the connection pads 16 being formed on first 18 and second 20 surfaces of the semiconductor device with edges of the semiconductor device 12 extending therebetween. A first passivation layer 22 is applied on the semiconductor device and a base dielectric laminate 42 is affixed to the first surface 18 of the semiconductor device that has a thickness greater than that of the first passivation layer 22. A second passivation layer having a thickness greater than that of the first passivation layer is applied over the first passivation layer and the semiconductor device to cover the second surface 20 and the edges of the semiconductor device 12, and metal interconnects are coupled to the connection pads, with the metal interconnects extending through vias formed through the first and second passivation layers and the base dielectric laminate 42 sheet to form a connection with the connection pads.