Multi-Chip Semiconductor Package Side-Fill for Thermal Stress Cracks
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Solution Overview
Problem
Semiconductor packages with multiple chips are prone to stress due to mismatched thermal expansion coefficients, leading to defects such as cracks, which decrease their reliability.
Innovation Solution
The semiconductor package design includes an interposer substrate with semiconductor chips facing each other, underfill parts, and side-fill parts extending along the chip edges and corners, utilizing a second side-fill part with a lower coefficient of thermal expansion to mitigate stress and prevent cracks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are mounted on the package to increase functionality, then the device complexity and functionality improve, but the thermal expansion mismatch stress increases leading to cracks and reduced reliability
Solution Approach 1:
The patent introduces a buffer layer as an intermediary component between the semiconductor chips and the package substrate. This buffer layer has a coefficient of thermal expansion that is intermediate between that of the chips and the substrate, serving as a stress-absorbing mediator that reduces thermal expansion mismatch stress and prevents crack propagation while allowing multiple chips to be mounted for enhanced functionality
Solution Approach 2:
The patent employs a composite structure consisting of multiple layers with different material properties, including the buffer layer, semiconductor chips, and package substrate. Each layer is selected with specific material characteristics to manage thermal expansion differences, creating a composite system that maintains structural integrity under thermal stress while supporting multi-chip configurations
2Adaptability or versatility
If the package size is increased to accommodate more semiconductor chips, then the functionality improves, but the stress from thermal expansion mismatch increases leading to cracks
Solution Approach 1:
The patent divides the package structure into segmented layers, including the buffer layer positioned between the chips and substrate. This segmentation allows each layer to independently manage stress, with the buffer layer specifically designed to absorb thermal expansion differences, enabling the package to accommodate multiple chips without compromising structural integrity
Solution Approach 2:
The patent changes the physical parameters of the package structure by introducing a buffer layer with specific mechanical and thermal properties. The buffer layer's coefficient of thermal expansion is deliberately selected to be intermediate between the chips and substrate, and its thickness and material composition are optimized to absorb stress while maintaining structural integrity across the entire package
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces stress-induced cracks, enhancing the reliability of the semiconductor package by minimizing thermal expansion mismatches between chips.
Implementation Method 1
the more semiconductor chips the semiconductor package covers, the larger size the semiconductor package has. As a size of a semiconductor package becomes larger, the semiconductor package may be vulnerable to stress generated due to a mismatch of coefficients of thermal expansion among individual components constituting the semiconductor package
Data Source
AI summary
A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.