Semiconductor Package Stacked Chip Direct Electrical Connection
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving improved electric characteristics and yield, particularly in multi-chip package techniques such as system-in-package (SiP) or package-in-package (PiP), where efficient electrical connections and testing are complex due to the integration of multiple semiconductor chips with different functions.
Innovation Solution
A semiconductor package design that includes a first semiconductor chip mounted on a package substrate with a chip package stacked on top, featuring a second semiconductor chip on a separate substrate, connected via multiple terminals and pads, allowing direct and efficient electrical connections, and incorporating test pads for easy testing and high yield manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-chip package techniques (SiP or PiP) are used to integrate multiple semiconductor chips with different functions into a single package structure, then the functional integration and miniaturization are improved, but the electrical connection complexity and manufacturing difficulty increase
Solution Approach 1:
The package structure is segmented into distinct functional layers: a first package substrate for mounting the first semiconductor chip, and a second package substrate for mounting the second semiconductor chip. This segmentation allows independent optimization of each substrate's pad layout and electrical connections, reducing overall complexity while maintaining high functional integration.
Solution Approach 2:
The patent transitions from planar pad arrangements to a three-dimensional stacked configuration. The first and second package substrates are vertically stacked with corresponding pads positioned at different heights (Z-axis), enabling electrical connections between chips in the vertical dimension rather than requiring extensive lateral routing on a single plane.
2Quantity of substance
If multiple pads are arranged closely to support high integration density, then the chip integration density is improved, but the manufacturing precision and yield decrease due to difficulty in testing and assembly
Solution Approach 1:
The pad structures are segmented into two separate package substrates with different pitch specifications. The first package substrate can have fine-pitch pads for high-density chip mounting, while the second package substrate can have coarse-pitch pads that are easier to test and assemble, thereby maintaining high integration density without sacrificing manufacturing yield.
Solution Approach 2:
Different regions of the package structure have different pad pitches optimized for their specific functions. The first package substrate area requires high density, so it uses smaller pitch pads, while the second package substrate area prioritizes manufacturability, so it uses larger pitch pads. This local optimization allows each region to have the quality it needs without compromising the other.
3Speed
If direct electrical connections are established between stacked chips, then the operational speed is improved, but the device complexity and difficulty of ensuring connection reliability increase
Solution Approach 1:
The first and second package substrates act as intermediary structures that facilitate reliable electrical connections between the stacked semiconductor chips. The substrates provide mechanically robust pad structures and controlled impedance transmission lines, serving as stable intermediaries that ensure signal integrity and connection reliability while enabling the fast direct chip-to-chip connections.
4Ease of manufacture
If test pads are electrically connected to connection pads with the same pitch, then the manufacturing process is simplified, but the testing capability and diagnostic precision are limited
Solution Approach 1:
The test pads and connection pads are designed with asymmetric pitch characteristics. The connection pads have a first pitch optimized for high-density signal routing, while the test pads have a second pitch (different from the first) that is optimized for probe card accessibility and testing accuracy. This asymmetric design allows each pad type to be optimized for its specific function rather than being constrained by a uniform pitch requirement.
Data Source
AI summary
Provided is a semiconductor package and a chip package of the same. The semiconductor package includes: a first semiconductor chip mounted on a first package substrate; a chip package stacked on the first semiconductor chip; and a first terminal connecting the chip package directly and electrically to the first semiconductor chip, wherein the chip package includes a second semiconductor chip mounted on a second package substrate, and the second package substrate includes a first pad coupled to the first terminal and a second pad electrically connected to the first pad and electrically spaced apart from the first terminal.