Semiconductor Package Vertical Stacking and Thermal Management
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving miniaturization, higher speed, and reduced transmission loss, particularly in integrating semiconductor chips with efficient electrical connections and heat management, while maintaining design flexibility and memory capacity.
Innovation Solution
The method involves forming a semiconductor package with vertically stacked memory dies and logic dies, using through insulator vias (TIVs) and a redistribution structure for electrical connectivity, and incorporating a heat sink for thermal management, allowing for increased memory capacity without expanding horizontal footprint and providing greater design flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor chips are bonded to a circuit carrier for electrical connections, then electrical connectivity is achieved, but transmission loss and insertion loss increase
Solution Approach 1:
The patent transitions from horizontal bonding of semiconductor chips to a circuit carrier to a vertical stacking architecture where memory dies and logic dies are stacked in the Z-dimension. Through-silicon vias (TSVs) provide vertical electrical interconnections, eliminating the need for horizontal trace routing on a circuit carrier. This dimensional change reduces transmission loss by shortening current paths and removing intermediate bonding interfaces.
2Quantity of substance
If memory capacity is increased by adding more chips, then storage capacity improves, but horizontal footprint expands
Solution Approach 1:
The patent stacks multiple memory dies vertically in the Z-dimension rather than placing them side-by-side in the X-Y plane. This vertical integration achieves high memory capacity (e.g., 128GB, 256GB) within a compact footprint by utilizing the third dimension. The stacked architecture maintains a small horizontal footprint while dramatically increasing storage capacity through multi-layer die stacking.
Solution Approach 2:
The patent implements a nested structure where multiple memory dies are stacked within a single package footprint, with each die containing memory arrays and shared control logic. The vertical stacking creates a nested arrangement where dies are positioned one above another, sharing common TSV interconnect structures and control units, thereby maximizing memory capacity within a confined horizontal area.
3Volume of moving object
If chip size is reduced for miniaturization, then device size decreases, but heat management becomes more difficult
Solution Approach 1:
The patent introduces an intermediary thermal management structure between the stacked dies and the external environment. A heat spreader or thermal interface material is positioned between the logic die and the heat sink, facilitating efficient heat transfer. The heat sink is attached to the bottom of the stacked assembly, providing a dedicated thermal pathway that conducts heat away from the compact vertical structure, thereby managing thermal density in miniaturized devices.
4Quantity of substance
If vertical stacking of dies is implemented, then memory capacity increases within constant footprint, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by pre-forming TSVs and bonding pads on memory dies before stacking. The TSVs are etched, lined, and filled with conductive material in advance, and bonding pads are prepared on the die surfaces prior to assembly. This preliminary preparation of interconnect structures simplifies the subsequent stacking process, as dies can be directly bonded using established flip-chip or wire bonding techniques without requiring complex in-situ interconnect formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical performance by reducing transmission loss, supports miniaturization, and allows for increased memory capacity within a constant footprint, while enabling more flexible design and efficient heat management.
Implementation Method 1
incorporating a heat sink for thermal management
Implementation Method 2
heat sink for thermal management
Data Source
AI summary
A semiconductor package includes a redistribution structure, a memory wafer, semiconductor dies and conductive vias. The memory wafer, disposed over the redistribution structure, includes at least one memory die. The semiconductor dies are disposed side by side with respect to each other, between the memory wafer and the redistribution structure, and are electrically connected to the redistribution structure. The conductive vias electrically connect the at least one memory die with the redistribution structure. A semiconductor package includes a redistribution structure, a reconstructed wafer, and a heat sink. The reconstructed wafer is disposed on the redistribution structure. The reconstructed wafer includes logic dies and memory dies. The logic dies are electrically connected to the redistribution structure. The memory dies are electrically connected to the redistribution structure and vertically stacked with the logic dies. The heat sink is disposed on the reconstructed wafer. The heat sink is fastened to the reconstructed wafer.