Semiconductor Package Stacking Dies Without Interposer
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Solution Overview
Problem
Conventional semiconductor packages face challenges in miniaturization due to the need for multiple dies with different functions, which require a large interposer, leading to increased size and signal transmission delays.
Innovation Solution
A semiconductor package design that stacks semiconductor dies of varying sizes without an interposer, using through-silicon vias and redistribution layers for electrical connectivity, allowing for alternately sized dies to be stacked and reducing package size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer is used to electrically connect multiple semiconductor dies with different functions and areas, then electrical connectivity between dies is achieved, but the package size increases and signal transmission speed is delayed
Solution Approach 1:
The patent removes the interposer from the package structure entirely. Instead of using an interposer to electrically connect semiconductor dies with different functions and areas, the invention directly stacks the dies on top of each other with electrical connections established through the die interfaces, eliminating the intermediate component that was causing size increase and signal delay
Solution Approach 2:
The patent transitions from a planar arrangement where dies are connected through an interposer to a three-dimensional stacked arrangement. By stacking dies vertically in multiple layers, the invention achieves electrical connectivity without requiring a large-area interposer, thus reducing package footprint while maintaining functional connectivity
2Reliability
If an interposer is disposed in the semiconductor package to connect multiple semiconductor dies, then electrical connectivity is achieved, but signal transmission speed is delayed
Solution Approach 1:
The patent removes the interposer from the signal path. By eliminating this intermediate component, electrical signals can be transmitted directly between semiconductor dies through their interfaces without passing through the interposer, thereby reducing transmission distance and improving signal speed
Solution Approach 2:
The patent eliminates the interposer as an intermediary component in the electrical connection path. Instead of using the interposer as a mediator to connect dies, the invention establishes direct electrical connections between adjacent dies in the stack, removing the mediating element that caused signal delay
3Adaptability or versatility
If multiple semiconductor dies with different functions and areas are connected through an interposer, then multi-functionality is achieved, but the package cannot be miniaturized
Solution Approach 1:
The patent uses vertical stacking to arrange multiple semiconductor dies with different functions and areas in three-dimensional space. This vertical arrangement allows diverse functional dies to be integrated without requiring a large planar area, enabling multi-functionality while achieving package miniaturization
Solution Approach 2:
The patent stacks semiconductor dies in a nested-like vertical configuration where smaller dies can be positioned on top of larger dies. This nested arrangement optimizes space utilization, allowing multiple functional dies to be integrated in a compact vertical structure rather than spreading them out horizontally
4Area of stationary object
If semiconductor dies of varying sizes are stacked without an interposer, then package size is reduced and signal speed is improved, but electrical connectivity and stress distribution become more challenging
Solution Approach 1:
The patent applies local quality by implementing electrical connections and stress management strategies specifically at the interfaces between stacked dies of varying sizes. Each die interface is designed with appropriate connection structures and stress distribution features tailored to the specific size mismatch at that location, rather than using a uniform approach throughout the package
Data Source
AI summary
Provided is a semiconductor package including first to third semiconductor dies, first to third RDL layers, conductive vias and an encapsulant, and a manufacturing method thereof. The first RDL layer is on an active surface of the first semiconductor die. The second semiconductor die is on the first RDL layer and electrically connected thereto through first TSVs. The conductive vias are on the first RDL layer and around the second semiconductor die. The encapsulant encapsulates the second semiconductor die and the conductive vias. The second RDL layer is on the encapsulant. The third semiconductor die is on the second RDL layer and electrically connected thereto through second TSVs. The third RDL layer is on the third semiconductor die. The area of the second semiconductor die is smaller than that of the first semiconductor die. The area of the third semiconductor die is larger than that of the second semiconductor die.