Semiconductor Package Stacking Design for Height Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturization and mounting reliability, particularly in stacking semiconductor chips, as existing stacking techniques are limited in reducing package height and require high precision, which hinders the development of high-capacity semiconductor modules.
Innovation Solution
A semiconductor package design that includes a substrate with lead members, a first semiconductor chip disposed face-up between lead members, and a second semiconductor chip disposed either face-up or face-down over the first chip, connected via conductive members, with a molding member encapsulating the components to minimize warpage and enhance mechanical and electrical reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If stacking two separate packages is used, then mounting reliability is improved, but package height cannot be sufficiently reduced
Solution Approach 1:
The patent merges multiple semiconductor chips and their interconnection structures into a single integrated package. The lead frame structure combines multiple lead members that can simultaneously connect multiple chips, eliminating the need for separate packages and reducing overall package height while maintaining mounting reliability through the integrated connection system.
Solution Approach 2:
The patent implements a nested structure where semiconductor chips are stacked vertically and interconnected through lead members that extend through multiple layers. The lead frame nested structure allows multiple chips to be housed within a compact vertical arrangement, reducing package height while maintaining reliable electrical connections between all components.
2Quantity of substance
If high integration of memory chip is achieved by increasing cells in limited space, then capacity is improved, but manufacturing precision requirements increase and development period lengthens
Solution Approach 1:
The patent transitions from planar integration to three-dimensional stacking architecture. Instead of increasing cell density in a two-dimensional plane which requires finer line widths, the invention stacks multiple chips vertically and connects them through lead members, achieving high capacity through the third dimension while using standard manufacturing precision for chip fabrication and interconnection.
3Volume of moving object
If chip stack package is used, then miniaturization and weight reduction are achieved, but warpage control becomes more difficult
Solution Approach 1:
The patent employs lead members with varying local properties - some lead members have higher flexibility to accommodate thermal expansion differences and prevent warpage, while others provide rigid structural support. The lead frame structure includes support portions and connection portions with different mechanical properties tailored to their specific functions, enabling miniaturization while controlling warpage through localized material property optimization.
Data Source
AI summary
A semiconductor package includes: a plurality of lead members disposed with a space therebetween over a surface of a substrate, a first semiconductor chip disposed in a face-up manner over the first surface of the substrate between at least two of the plurality of lead members; a second semiconductor chip disposed in a face-up manner over the first semiconductor chip and the at least two lead members, and a connection member for connecting the substrate, the at least two lead members, the first semiconductor chip and the second semiconductor chip with one another.