Semiconductor Package Stacking for Signal Path Optimization
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Solution Overview
Problem
The existing connection systems for semiconductor packages face challenges in efficiently connecting application processors (AP) and memory packages without using separate interposers or backside redistribution layers, and in optimizing the placement of power management ICs (PMICs) for reduced power paths and heat dissipation.
Innovation Solution
A connection system where the PMIC package is stacked on top of the AP package in a package-on-package (POP) form, both mounted on one surface of a printed circuit board, with the memory package mounted on the opposite surface, eliminating the need for separate interposers or backside redistribution layers and allowing for optimized power management and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an interposer or backside redistribution layer is used to connect memory package and AP package, then the connection between memory and AP is achieved, but the device complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the interposer and backside redistribution layer from the connection system. By directly mounting the memory package on the AP package using solder balls, the complex intermediate structures are removed, simplifying the overall device while maintaining reliable electrical connection between memory and AP.
Solution Approach 2:
The patent merges the mounting functions by directly attaching the memory package to the AP package through solder balls. This consolidation eliminates separate interposer and redistribution layer components, creating a more integrated and simpler structure that reduces both device complexity and manufacturing cost.
2Reliability
If PMIC is disposed separately from AP package and memory package, then power management function is achieved, but the power path length increases and heat dissipation efficiency decreases
Solution Approach 1:
The patent implements nesting by placing the PMIC package inside or integrated with the AP package structure. This nested arrangement allows the PMIC to be positioned close to the AP, creating a short power path while maintaining effective power management functions, thereby reducing energy loss and improving heat dissipation efficiency.
Solution Approach 2:
The PMIC package serves as an intermediary component that is strategically positioned between the power source and the AP. By integrating it within the AP package rather than placing it separately, the power path is optimized for efficiency while the PMIC continues to perform its mediating power management functions effectively.
3Quantity of substance
If memory package has large number of I/Os, then memory capacity and performance are increased, but the signal path length increases when connected through separate interposer
Solution Approach 1:
The patent extracts the signal path optimization by eliminating the interposer from the connection architecture. By directly connecting memory package I/Os to the AP package through solder balls, the signal paths are shortened despite the large number of I/Os, improving signal integrity and reducing transmission delays.
Solution Approach 2:
The patent transitions from a planar connection approach through interposer to a vertical stacking architecture. By mounting the memory package directly on the AP package in a three-dimensional configuration, the signal paths are optimized by reducing lateral traversal distance, effectively managing the large number of I/O connections with shorter signal paths.
Data Source
AI summary
A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first 10 semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated 15 circuit (PMIC).