Semiconductor Package 3D Stacking Reduces Warpage
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Solution Overview
Problem
Current semiconductor packages face challenges in maximizing space utilization, reducing size, and minimizing warpage while ensuring reliable electrical connections between semiconductor chips and passive elements.
Innovation Solution
The semiconductor package design incorporates a first semiconductor chip with a redistribution structure, a second semiconductor chip, conductive posts, and a molding layer, where the second semiconductor chip and passive elements are mounted in one area and conductive posts in another, allowing for efficient space use and reduced size, with a deformation prevention structure to minimize warpage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If semiconductor chips and passive elements are mounted on a substrate, then functional integration is achieved, but space utilization is insufficient and package size increases
Solution Approach 1:
The patent transitions from planar mounting to three-dimensional stacking, placing the second semiconductor chip vertically above the first semiconductor chip. This vertical arrangement utilizes the Z-dimension (height) rather than only the X-Y plane, thereby increasing functional integration while reducing the lateral footprint and overall package size.
Solution Approach 2:
The patent implements a nested configuration where the second semiconductor chip is positioned within the vertical space above the first semiconductor chip. The redistribution structures and conductive posts create a nested hierarchy of electrical connections, with inner layers connected to outer layers through vertical conductive paths, maximizing space utilization.
2Adaptability or versatility
If components are arranged to maximize integration, then functional capability increases, but manufacturing complexity increases
Solution Approach 1:
The patent divides the substrate surface into distinct mounting areas: a first area for the second semiconductor chip and passive elements, and a second area for conductive posts. The redistribution structure is segmented into multiple layers (first redistribution structure and second redistribution structure) with defined functional zones, simplifying the manufacturing process by providing clear spatial guidelines for component placement.
Solution Approach 2:
The redistribution structures serve as intermediary elements that facilitate electrical connections between different components. The first redistribution structure connects the first semiconductor chip to the second semiconductor chip and passive elements, while the second redistribution structure provides additional routing layers. These intermediaries simplify the overall connection architecture by providing dedicated connection paths.
3Adaptability or versatility
If electrical connections are extended between chips and passive elements, then functional connectivity is achieved, but electrical path distance increases
Solution Approach 1:
The patent utilizes vertical conductive posts to establish electrical connections between the first semiconductor chip, second semiconductor chip, and passive elements. By transitioning from lateral routing to vertical routing through the Z-dimension, the electrical path distance is significantly reduced compared to traditional planar routing methods.
Solution Approach 2:
The conductive posts act as intermediary elements that provide direct vertical electrical pathways between different mounting areas. The first redistribution structure and second redistribution structure serve as mediators that route signals efficiently between components, minimizing the electrical path length by providing dedicated connection channels rather than requiring long lateral traces.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first surface and a second surface, and including a first active layer on a portion adjacent to the first surface; a first redistribution structure on the first surface of the first semiconductor chip, wherein the first redistribution structure includes a first area and a second area next to the first area; a second semiconductor chip mounted in the first area of the first redistribution structure, including a third surface, which faces the first surface, and a fourth surface, and including a second active layer on a portion adjacent to the third surface; a conductive post mounted in the second area of the first redistribution structure; a molding layer at least partially surrounding the second semiconductor chip and the conductive post on the first redistribution structure; and a second redistribution structure disposed on the molding layer and connected to the conductive post.