Semiconductor Package Support Structure for Reliable Redistribution Routing
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in ensuring the reliability and efficiency of electrical connections and structural integrity of semiconductor packages, particularly in wafer-level packaging processes.
Innovation Solution
A manufacturing method involving the use of a debond layer, dielectric layers, seed layers, and redistribution circuit structures, along with supporting structures and under-bump metallurgy patterns, to enhance the electrical connections and structural integrity of semiconductor packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wafer-level packaging is used, then manufacturing simplicity is maintained, but electrical connection reliability and structural integrity deteriorate
Solution Approach 1:
The packaging structure is segmented into multiple functional layers including dielectric layers, conductor patterns, and supporting structures. Each layer performs a specific function: dielectric layers provide insulation, conductor patterns establish electrical connections, and supporting structures maintain structural integrity. This segmentation allows complex functionality to be achieved while maintaining manufacturing feasibility through standardized layer-by-layer fabrication processes.
Solution Approach 2:
The patent transitions from traditional planar wafer-level packaging to a three-dimensional stacked architecture. Multiple conductor patterns are formed at different vertical levels within the encapsulant, creating vertical electrical interconnections. This dimensional transition enables complex electrical routing and improved connection reliability while maintaining a compact package footprint.
2Reliability
If complex multi-layer structures are added to improve electrical connections, then connection reliability improves, but manufacturing complexity increases
Solution Approach 1:
The dielectric layers serve multiple functions simultaneously: they provide electrical insulation between conductor patterns, mechanically support the fragile semiconductor die, and create a structured framework for forming vertical interconnections. This multi-functionality reduces the need for additional specialized components and simplifies the overall manufacturing process despite the multi-layer complexity.
Solution Approach 2:
The conductor patterns are pre-formed within the dielectric layers before the semiconductor die is attached. This preliminary formation of electrical interconnection structures allows subsequent bonding and wire bonding steps to focus solely on connecting to existing pads, rather than forming complex three-dimensional interconnections during assembly, thereby simplifying the manufacturing process.
3Strength
If supporting structures are added to improve structural integrity, then package strength improves, but device complexity increases
Solution Approach 1:
The supporting structures are merged with the existing dielectric and conductor layer architecture rather than being added as separate external components. The supporting structures utilize the same materials and fabrication processes as the interconnection layers, integrating structural reinforcement functionality into the existing multi-layer system. This merging approach improves structural integrity without proportionally increasing manufacturing complexity.
Data Source
AI summary
A semiconductor package includes a semiconductor die, a redistribution circuit structure, a supporting structure and a protective layer. The redistribution circuit structure is located on and electrically coupled to the semiconductor die. The supporting structure is located on an outer surface of the redistribution circuit structure, wherein the supporting structure is overlapped with at least a part of the semiconductor die or has a sidewall substantially aligned with a sidewall of the semiconductor die in a vertical projection on the redistribution circuit structure along a stacking direction of the redistribution circuit structure and the supporting structure. The protective layer is located on the supporting structure, wherein the supporting structure is sandwiched between the protective layer and the redistribution circuit structure.