Semiconductor Package Thermal Conductive Layer Design
Solution Overview
Problem
Current semiconductor packages face challenges in achieving high reliability and efficient heat dissipation while maintaining miniaturization and multifunctionality, particularly in redistributing connection terminals and managing thermal conductivity effectively.
Innovation Solution
A semiconductor package design that includes a semiconductor chip with a thermal conductive layer and a redistribution structure, featuring a core layer with through-holes for mounting, a sealing layer, and upper and lower wiring layers for enhanced thermal dissipation and electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a thermal conductive layer with higher thermal conductivity than the semiconductor chip is introduced, then heat dissipation efficiency is improved, but package structure complexity increases
Solution Approach 1:
The package structure is segmented into distinct functional layers: the semiconductor chip layer, the thermal conductive layer with higher thermal conductivity material, and the molding compound layer. This segmentation allows each layer to perform its specific function optimally, with the thermal conductive layer dedicated to heat dissipation while other layers handle electrical and protective functions.
Solution Approach 2:
The patent employs composite material structure by combining the semiconductor chip material with a thermal conductive layer made of different material having superior thermal conductivity properties. This composite approach allows the package to leverage the electrical properties of the semiconductor chip while utilizing the enhanced thermal conductivity of the specialized thermal conductive layer for effective heat dissipation.
2Reliability
If redistribution portions with multiple wiring layers are added, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The redistribution portions are implemented as multi-layer wiring structures extending in the vertical dimension rather than relying solely on planar routing. By stacking multiple wiring layers (first wiring layer, second wiring layer, etc.) at different heights and connecting them through vias, the design achieves complex electrical interconnections while efficiently utilizing the three-dimensional package space.
Solution Approach 2:
The multi-layer wiring structure employs a nested arrangement where multiple wiring layers are stacked one above another, with each layer containing conductive patterns that may be partially or fully enclosed by insulating layers. This nested configuration allows dense electrical interconnections to be achieved within a compact vertical footprint, improving connectivity without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves heat dissipation efficiency and package reliability by utilizing a thermal conductive layer with higher thermal conductivity than the semiconductor chip, effectively managing heat emission and reducing thermal resistance, even with increased package thickness.
Implementation Method 1
a thermal conductive layer disposed on the second surface of the semiconductor chip
Data Source
AI summary
A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.