Semiconductor Package Structure Using Through-Oxide Vias to Cut 3DIC Cost
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Solution Overview
Problem
The high manufacturing cost associated with forming hybrid bonding structures and through-silicon vias (TSVs) in current 3DIC stacking technologies for semiconductor wafers, which are necessary for high-performance computing and artificial intelligence applications, limits the cost-effectiveness of wafer stacking and electrical connections.
Innovation Solution
The use of through oxide vias (TOVs) for electrically connecting stacked semiconductor wafers, which simplifies the bonding process by eliminating the need for hybrid bonding structures and TSVs, and instead employs dielectric material for fusion bonding and conductive material filling within dielectric-filled trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hybrid bonding structures and through-silicon vias (TSVs) are used for connecting stacked semiconductor wafers, then electrical connection reliability is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent extracts and eliminates the complex hybrid bonding structure and TSV formation processes from the semiconductor packaging method. Instead of forming traditional TSVs through the silicon substrate, the invention uses through-oxide vias formed through the dielectric layer only, removing the costly and complex bonding and via formation steps while maintaining electrical connection functionality.
Solution Approach 2:
The patent replaces expensive, complex hybrid bonding structures with a simpler, more cost-effective through-oxide via approach. The dielectric-filled trench structure with conductive material provides the necessary electrical connection at a fraction of the cost of traditional TSV and hybrid bonding processes, sacrificing some structural complexity for significant cost reduction.
2Reliability
If through-silicon vias (TSVs) are formed for electrical connections, then connection performance is improved, but process complexity increases
Solution Approach 1:
The patent segments the via formation process by creating separate functional layers: a dielectric layer for mechanical support and insulation, a dielectric-filled trench for structural integrity, and a conductive material fill for electrical connection. This segmentation allows each layer to be optimized independently and formed through simpler, more manageable processes compared to monolithic TSV formation.
Solution Approach 2:
The patent introduces a dielectric-filled trench as an intermediary structure between the substrate and the conductive via. This dielectric material serves as a mediator that provides mechanical support, enables simpler via formation, and maintains electrical insulation where needed, while allowing conductive material to be deposited in a controlled manner for reliable electrical connection.
3Reliability
If hybrid bonding structures are used for wafer stacking, then stacking reliability is improved, but manufacturing simplicity deteriorates
Solution Approach 1:
The patent extracts the bonding function from the via formation process. Instead of forming hybrid bonding structures that require precise alignment and complex thermal processing, the invention uses through-oxide vias that can be formed through standard semiconductor fabrication processes, eliminating the need for separate bonding steps and simplifying the overall manufacturing flow.
Solution Approach 2:
The patent changes the material parameters and process conditions by using oxide-based dielectric materials and standard conductive fill processes instead of requiring precise hybrid bonding parameters. This allows the use of conventional semiconductor manufacturing equipment and processes, significantly improving manufacturing simplicity while maintaining stacking reliability through the robust dielectric-filled trench structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and enhances the cost-effectiveness of semiconductor package structures by simplifying the bonding process and electrical connections, allowing for efficient stacking of integrated circuits without the high costs associated with traditional TSV formation.
Implementation Method 1
the through via structure includes a conductive material
Implementation Method 2
the through via structure includes a conductive material
Implementation Method 3
employs dielectric material for fusion bonding
Data Source
AI summary
A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor structure, a dielectric bonding structure, a second semiconductor structure, and a through via structure. The first semiconductor structure includes a first substrate and a first back-end-of-line (BEOL) structure over the first substrate. The dielectric bonding structure is over the first semiconductor structure. The second semiconductor structure is over the dielectric bonding structure. The second semiconductor structure includes a second BEOL structure over the dielectric bonding structure and a second substrate over the second BEOL structure. The through via structure penetrates the second semiconductor structure and the dielectric bonding structure to connect the first BEOL structure and the second BEOL structure. A method for forming a semiconductor package structure is also provided.