Semiconductor Package Layout for Wire Bond and TSV Integration
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Solution Overview
Problem
The use of through silicon vias in wire bonding structures for image sensor products increases the size of the camera module, necessitating additional space and potentially compromising the aesthetics and usability of the semiconductor package.
Innovation Solution
A semiconductor package design that incorporates a silicon substrate with through openings and a redistribution wiring layer featuring distinct pad areas and redistribution wires, allowing for both bonding wires and through silicon vias to be selectively included, thereby optimizing space utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a through silicon via structure is used in the wire bonding structure, then electrical connection is achieved, but additional space is required and the semiconductor package size increases
Solution Approach 1:
The patent implements a dual-connection structure where the semiconductor package can be electrically connected through either bonding wires or through silicon vias. The redistribution wiring layer includes both bonding pads for wire bonding and landing pads for through silicon via connections, making the package universally compatible with both connection methods and allowing selection based on space constraints.
Solution Approach 2:
The patent creates a dynamic configuration where the connection method can be selectively determined. The package structure accommodates variable connection approaches - wire bonding for larger packages or through silicon vias for space-constrained applications - allowing the electrical connection method to adapt to different packaging requirements and space availability.
2Reliability
If wire bonding structure is used, then electrical connection is achieved, but package size cannot be reduced further
Solution Approach 1:
The patent implements a dual-connection structure where the semiconductor package can be electrically connected through either bonding wires or through silicon vias. The redistribution wiring layer includes both bonding pads for wire bonding and landing pads for through silicon via connections, making the package universally compatible with both connection methods and allowing selection based on space constraints.
Solution Approach 2:
The patent changes the connection parameter from exclusively wire bonding to a selectable between wire bonding and through silicon via. This parameter change enables optimization of the package size by choosing the more space-efficient through silicon via method when camera module size reduction is the priority.
Data Source
AI summary
A semiconductor package includes a silicon substrate including a plurality of through openings, and a redistribution wiring layer including a first surface and a second surface opposite the first surface, the second surface facing the silicon substrate, the redistribution wiring layer including a first pad area and a second pad area. The redistribution wiring layer includes a plurality of bonding pads on the first pad area at the first surface, a plurality of test pads on the second pad area at the first surface, a plurality of landing pads on the second pad area at the second surface, the plurality of landing pads in communication with the plurality of through openings, respectively, and a plurality of redistribution wires electrically connected to the plurality of bonding pads and the plurality of landing pads.