Semiconductor Package Layer Stack for Warpage and Twist Control
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Solution Overview
Problem
The challenge in semiconductor packaging is to achieve compact and efficient integration of electronic components while addressing issues such as warpage and twisting, which are not adequately resolved by existing technologies.
Innovation Solution
A method involving a redistribution layer (RDL) structure with alternating polymer and redistribution layers, encapsulation, and a protection layer to control warpage, combined with through integrated vias (TIVs) and caps to protect against oxidation, facilitating efficient electrical connections and package-on-package (PoP) integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If integrated fan-out packages are used to achieve compactness, then package size is reduced, but warpage and twisting issues arise
Solution Approach 1:
The package structure is divided into multiple functional layers including RDL structure, encapsulant, protection layer, and interlayer dielectric. Each layer serves specific functions to manage stress and prevent warpage while maintaining compact size. The segmentation allows independent optimization of each layer for both size reduction and stability.
Solution Approach 2:
The patent employs composite material structures including alternating polymer and redistribution layers, encapsulant materials, and protection layers with different mechanical properties. These composite structures balance thermal expansion coefficients and mechanical stresses to minimize warpage and twisting in the compact package.
2Reliability
If RDL structure with alternating polymer and redistribution layers is implemented, then electrical connections are improved, but manufacturing complexity increases
Solution Approach 1:
The RDL structure with alternating polymer and redistribution layers is formed in advance before final packaging. This preliminary formation of the electrical connection structure allows for better control and inspection before subsequent packaging steps, improving overall manufacturing efficiency despite the complex multi-layer structure.
Solution Approach 2:
The RDL structure serves multiple functions: electrical redistribution, mechanical support, and stress management. By integrating these functions into a single multi-layer structure, the patent reduces the need for separate components, thereby managing manufacturing complexity while improving electrical connection reliability.
3Reliability
If through integrated vias (TIVs) and caps are added to protect against oxidation, then reliability is improved, but device complexity increases
Solution Approach 1:
The caps formed over the TIVs provide self-contained protection against oxidation without requiring additional active maintenance or external protective systems. The structural design inherently provides protection through the cap formation, eliminating the need for separate protective mechanisms and reducing overall system complexity.
Solution Approach 2:
The TIVs and caps are integrated into the existing package structure rather than being added as separate external components. The caps are formed as part of the layer stack, merging the protective function with the structural layers, thereby minimizing additional complexity while improving reliability.
Data Source
AI summary
A method of forming a semiconductor device includes the following steps. A die and a first through via aside the die are formed. An encapsulant is formed to encapsulate the die and the first through via, wherein the encapsulant is physically connected to a sidewall of the first through via and a sidewall of the die. A warpage controlling layer is formed over the encapsulant and the die. A first conductive connector is formed on the first through via to electrically connect to the first through via.