Semiconductor Package Structure Eliminating Underfill via Molding Compound

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Solution Overview

Problem

New packaging technologies for semiconductor devices, such as package on package (PoP), face manufacturing challenges and have not been entirely satisfactory in all respects, particularly in terms of integration and reliability.

Innovation Solution

A package structure and method involving a carrier substrate, adhesive layer, redistribution structure with conductive and passivation layers, and a molding compound layer that encapsulates conductive features and integrated circuit dies, allowing for efficient bonding and encapsulation without the need for underfill materials, thereby enhancing design flexibility and reducing fabrication time and cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If traditional packaging methods with underfill materials are used, then structural support is provided, but manufacturing complexity and fabrication time increase

Engineering Contradiction:

Improvestructural supportVSAvoidmanufacturing complexity

Core Design Contradiction:

StrengthVSDevice complexity

Solution Approach 1:

The patent removes the underfill material layer from the package structure, eliminating the need for this additional component while maintaining structural integrity through the molding compound that directly encapsulates the die and conductive features

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent combines the functions of structural support and encapsulation into a single molding compound layer, merging what were previously separate functions (underfill for support, molding compound for encapsulation) into one integrated solution

Inventive Principle:

Principle #5Merging (Combining)

2Reliability

If underfill materials are used in packaging, then die attachment is supported, but fabrication time and cost increase

Engineering Contradiction:

Improvedie attachmentVSAvoidfabrication time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent eliminates the underfill material step from the fabrication process, removing the associated time and cost while maintaining die attachment reliability through direct bonding to the substrate

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs die attachment to the substrate before forming the molding compound, establishing the structural foundation in advance and eliminating the need for subsequent underfill application steps

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If conventional packaging processes are used, then manufacturing is straightforward, but integration density and device performance are limited

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidintegration density

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent transitions from planar packaging to three-dimensional integration by stacking multiple dies vertically with conductive features extending through the structure, enabling higher integration density while maintaining manufacturing feasibility

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where conductive features are embedded within the molding compound, which in turn encapsulates the dies, creating multiple hierarchical levels of integration within a compact volume

Inventive Principle:

Principle #7Nested doll (Nesting)

4Adaptability or versatility

If more connectors are added to increase I/O connections, then device functionality improves, but package area increases

Engineering Contradiction:

Improvenumber of input/output connectionsVSAvoidpackage area

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent utilizes the vertical dimension by extending conductive features through the molding compound and stacking dies vertically, allowing increased I/O connections without proportionally increasing the horizontal package footprint

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10658334B2Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die

Publication Date: 2020.05.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Package structures and methods for forming the same are provided. The method includes providing a first integrated circuit die and forming a redistribution structure over the first integrated circuit die. The method also includes forming a base layer over the redistribution structure. The base layer has first and second openings. The first openings are wider than the second openings. The method further includes forming first bumps over the redistribution structure. The first bumps have a lower portion filling the first openings. In addition, the method includes bonding a second integrated circuit die to the redistribution structure through second bumps having a lower portion filling the second openings. There is a space between the second integrated circuit die and the base layer. The method also includes forming a molding compound layer over the base layer. The molding compound layer fills the space and surrounds the first and second bumps.