3D Semiconductor Package Structure with Underfill and TSVs
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Solution Overview
Problem
The semiconductor industry faces challenges in efficiently packaging high-density electronic components due to the need for smaller packages that occupy less area, while maintaining mechanical support and electrical connectivity, especially in three-dimensional integrated circuits (3DICs) and package-on-package (PoP) devices.
Innovation Solution
A method of forming package structures using a carrier with a de-bonding layer, dielectric layers, conductive vias, and redistribution layers, where package units are separated by scribe regions, allowing for mechanical support, electrical connectivity, and efficient encapsulation, with an underfill layer filling the gaps between components and substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If smaller packages are used to reduce area occupation, then area is reduced, but mechanical support and electrical connectivity become more difficult to maintain
Solution Approach 1:
The patent transitions from two-dimensional planar packaging to three-dimensional vertical stacking with multiple tiers. Multiple semiconductor components are stacked vertically and connected through through-silicon vias (TSVs), enabling high-density integration while maintaining structural integrity through vertical rather than horizontal expansion.
Solution Approach 2:
The package structure is divided into multiple discrete tiers, each containing semiconductor components, interconnection structures, and encapsulant layers. This segmentation allows independent optimization of each tier while maintaining overall mechanical support and electrical connectivity through standardized inter-tier connections.
2Area of stationary object
If smaller packages are used to reduce area occupation, then area is reduced, but electrical connectivity becomes more difficult to maintain
Solution Approach 1:
Electrical connectivity is achieved through vertical three-dimensional interconnections using through-silicon vias (TSVs) that penetrate through semiconductor substrates. This vertical routing approach enables compact packaging while maintaining reliable electrical connections between stacked components without requiring large horizontal trace lengths.
Solution Approach 2:
Multiple interconnection structures are nested within the vertical stack, with TSVs embedded in encapsulant layers that are themselves embedded in subsequent tiers. This nested arrangement allows multiple electrical connection paths to be integrated within the compact three-dimensional structure, maintaining connectivity while minimizing package area.
3Productivity
If multiple semiconductor components are integrated in high density, then integration density is improved, but fabrication complexity increases
Solution Approach 1:
Through-silicon vias (TSVs) and interconnection structures are formed within semiconductor substrates before the substrates are stacked and bonded together. This preliminary formation of interconnections simplifies the overall fabrication process by eliminating the need for complex post-bonding alignment and connection operations, thereby reducing fabrication complexity while enabling high integration density.
Solution Approach 2:
The fabrication process is divided into discrete steps for forming individual tiers with their respective semiconductor components and interconnection structures. Each tier can be fabricated and prepared independently before assembly, allowing parallel processing and simplifying the overall manufacturing workflow while achieving high integration density through vertical stacking.
Data Source
AI summary
A package structure and method of forming the same are provided. The package structure includes a semiconductor unit, a package component and an underfill layer. The semiconductor structure unit includes a first semiconductor structure and a second semiconductor structure disposed as side by side, and an isolation region laterally between the first semiconductor structure and the second semiconductor structure. The isolation region vertically extends from a top surface to a bottom surface of the semiconductor structure unit. The semiconductor structure unit is disposed on and electrically connected to the package component. The underfill layer is disposed to fill a space between the semiconductor structure unit and the package component.