Semiconductor Package Via Interconnects for Density and Cost
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor package structures face challenges with wire bonding due to high power consumption, capacitance, and limited density of interconnections, while Through Silicon Via (TSV) methods are complex and costly with low yield.
Innovation Solution
A semiconductor package structure and manufacturing method involving a substrate, dielectric layers, and vias that penetrate through encapsulation layers to connect chips, allowing for increased interconnection density with reduced complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wire bonding is used for interconnections, then the method is simple and cost-effective, but the power consumption and capacitance increase due to long conductive paths
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional vertical vias. The conductive paths are moved from horizontal wire bonds on the chip surface to vertical vias penetrating through the chip thickness, utilizing the Z-dimension to achieve shorter conductive paths while maintaining manufacturing simplicity through established via formation processes
2Ease of manufacture
If wire bonding is used for interconnections, then the manufacturing process is simple, but the interconnection density is limited due to space requirements for wires, bumps and pads
Solution Approach 1:
The patent utilizes the vertical dimension by forming vias through the chip thickness, allowing multiple interconnections to be stacked vertically. This three-dimensional via architecture enables significantly higher interconnection density compared to planar wire bonding, as vias can be arranged in dense arrays without requiring large surface area for wire loops and bumps
Solution Approach 2:
The patent changes the geometric parameters of interconnections from long horizontal wires to short vertical vias. By altering the orientation and dimensions of conductive paths, the patent achieves higher density while maintaining manufacturing simplicity through standard via formation techniques
3Length of moving object
If Through Silicon Via (TSV) is used for interconnections, then the conductive path length is reduced and interconnection density is increased, but the manufacturing process becomes complex and costly with reduced yield
Solution Approach 1:
The patent employs a simplified via formation process that uses sacrificial materials and standard semiconductor fabrication techniques rather than complex TSV processes. The method uses disposable photomask patterns and sacrificial layers that are removed after via formation, achieving short conductive paths without the high complexity and cost of true TSV manufacturing
Data Source
AI summary
A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure comprises a substrate, a first chip, a first dielectric layer, a dielectric encapsulation layer and at least one first via. The first chip is disposed on the substrate. The first chip has a first landing area. The first dielectric layer is disposed on the first chip. The dielectric encapsulation layer encapsulates the first chip and the first dielectric layer. The at least one first via penetrates through the dielectric encapsulation layer and the first dielectric layer. The at least one first via connects to the first landing area of the first chip.