Semiconductor Package with Via Patterns in Encapsulation
Solution Overview
Problem
Current semiconductor packaging technologies face challenges in highly integrating semiconductor devices while minimizing the complexity and cost associated with through-silicon vias (TSVs), particularly in vertically stacking semiconductor chips, which increases manufacturing complexity and costs.
Innovation Solution
A semiconductor package design featuring first and second semiconductor chips arranged in a rotationally symmetrical structure with via patterns and encapsulation members to form step shapes, allowing electrical connections without the need for extensive TSVs, thereby simplifying the interconnect process and reducing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) are used to connect multiple semiconductor chips vertically, then electrical connections between chips are achieved, but manufacturing complexity and costs increase
Solution Approach 1:
The patent divides the interconnection structure into segments: via patterns are formed only in the encapsulation member rather than through the entire silicon substrate thickness. This segmentation allows electrical connections to be established at intermediate levels, reducing the need for deep through-silicon vias and simplifying the manufacturing process while maintaining reliable electrical connectivity between stacked chips
Solution Approach 2:
The encapsulation member serves as an intermediary structure that contains via patterns to facilitate electrical connections between chips. Instead of requiring direct through-silicon via connections, the encapsulation member acts as a mediator with integrated via patterns that enable signal transmission between lower and upper chips, reducing manufacturing complexity while ensuring reliable electrical interconnects
2Productivity
If multiple semiconductor chips are vertically stacked, then device integration is improved, but manufacturing costs increase
Solution Approach 1:
The patent merges the via formation process with the encapsulation process. Via patterns are formed within the encapsulation member during the encapsulation stage rather than requiring separate through-silicon via fabrication steps. This merging of processes reduces the total number of manufacturing steps, lowers equipment requirements, and decreases overall manufacturing costs while enabling effective vertical integration of multiple chips
Solution Approach 2:
The via patterns are formed in the encapsulation member rather than creating permanent through-silicon structures. This approach uses a less expensive, more easily fabricated structure (via patterns in encapsulation material)替代昂贵的through-silicon vias, achieving the same electrical connection function at lower manufacturing cost
Data Source
AI summary
A semiconductor package may include first semiconductor chips disposed in a rotationally symmetrical structure. First bonding pads are arranged over the bottom surfaces of the first semiconductor chips. The semiconductor package may also include a first encapsulation member formed to surround at least side surfaces of the first semiconductor chips. The semiconductor package may also include via patterns formed in the first encapsulation member. The semiconductor package may also include second semiconductor chips stacked over top surfaces of the first semiconductor chips and the first encapsulation member including the via patterns in such a way as to form step shapes with the first semiconductor chips. Second bonding pads electrically connected to the via patterns are arranged over bottom surfaces of the second semiconductor chips. The semiconductor package may also include a second encapsulation member formed over the top surfaces of the first semiconductor chips and the first encapsulation member to surround at least side surfaces of the second semiconductor chips.