Semiconductor Package Wire Routing via Substrate Vias
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Solution Overview
Problem
The increasing demand for compact semiconductor packages in miniaturized electronic products poses challenges in achieving high integration density and efficient chip attachment while maintaining package compactness and functionality.
Innovation Solution
A semiconductor package design featuring a film substrate with specific bonding and chip regions, including pad groups and wires that connect semiconductor chips to bonding regions, allowing for compact integration and efficient signal transmission between driver circuits and display panels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are bonded directly on a substrate by flip-chip bonding in a COF package, then fine wire patterns can be formed and high integration density is achieved, but the package size and chip-to-chip distance cannot be sufficiently reduced for compact electronic products
Solution Approach 1:
The patent transitions from planar wire patterns on a single surface to three-dimensional wire routing that utilizes both surfaces of the film substrate. Wires extend from the first surface through vias to the second surface, enabling vertical interconnections and reducing the need for lengthy lateral wire traces, thereby achieving compact packaging with high integration density
Solution Approach 2:
The patent implements a nested structure where vias penetrate through the film substrate to connect wire segments on different surfaces. The wire pattern includes first wires on the first surface, second wires on the second surface, and vias nesting through the substrate thickness to interconnect them, creating a compact multi-layer interconnection system that reduces package size while maintaining high integration
2Reliability
If wire patterns are extended along the first surface to connect pads to bonding regions, then electrical connection is established, but the package occupies larger area and reduced compactness is achieved
Solution Approach 1:
The patent utilizes the third dimension (substrate thickness) by routing wires along both the first and second surfaces of the film substrate and connecting them through vias. This vertical routing approach shortens the lateral wire length required to connect pads to bonding regions, reducing the package area while ensuring reliable electrical connections
Solution Approach 2:
The patent divides the wire interconnection path into multiple segments: first wires on the first surface, vias penetrating the substrate, and second wires on the second surface. This segmentation allows the interconnection to bypass long lateral routes and use vertical pathways through the substrate, reducing the overall package area while maintaining electrical connectivity
Data Source
AI summary
Semiconductor packages are provided. A semiconductor package includes a substrate including a first bonding region, a chip region, and a second bonding region. Moreover, the substrate includes first and second surfaces that are opposite to each other. The semiconductor package includes a pad group including a pad on the first surface in the chip region. The semiconductor package includes a semiconductor chip on the pad group. The semiconductor package includes a wire connecting the pad and the second bonding region. The wire includes a portion that extends along the second surface of the substrate. Related display devices are also provided.