Semiconductor Package With Through Interlayer Vias And Metal Ring
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in reducing the height and improving electrical performance of semiconductor packages while maintaining effective encapsulation and interconnectivity between redistribution layers and dies.
Innovation Solution
The semiconductor package design incorporates a molded semiconductor device with a first and second redistribution layer, where through interlayer vias electrically connect the layers, and a metal ring surrounds the interconnection circuit portion to enhance space utilization and reduce package size, using polymer-based dielectric materials and patterned metal layers for efficient electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional packaging structures are used, then encapsulation and interconnectivity are maintained, but package height is increased and electrical performance is degraded
Solution Approach 1:
The patent implements through-interlayer vias that extend vertically through the molding compound to establish electrical connections between the first and second redistribution layers. This vertical dimension approach enables shorter signal paths and reduced package height while maintaining effective electrical interconnectivity, resolving the contradiction between compact dimensions and electrical performance
Solution Approach 2:
The patent embeds the first die within the molding compound and nests the second redistribution layer over the molding compound, with through-vias penetrating through the molding compound to connect nested layers. This nested configuration achieves space utilization optimization and reduced package height while preserving electrical connections
2Volume of moving object
If package size is reduced, then space utilization improves, but structural reinforcement and operational reliability may be compromised
Solution Approach 1:
The patent employs a composite structure combining molding compound, metal redistribution layers, and conductive via materials. The metal ring surrounding the interconnection circuit portion provides structural reinforcement while the composite material system maintains package integrity in the reduced size configuration, resolving the contradiction between compact volume and structural strength
Solution Approach 2:
The patent divides the package into distinct functional segments: first redistribution layer, molding compound with embedded die, second redistribution layer with metal ring, and through-interlayer vias. This segmentation allows optimized space utilization for each component while maintaining overall structural reinforcement through the coordinated arrangement of segments
Data Source
AI summary
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution layer, a second redistribution layer, and a plurality of through interlayer vias. The molded semiconductor device includes a die. The first redistribution layer is disposed on a first side of the molded semiconductor device. The second redistribution layer is disposed on a second side of the molded semiconductor device opposite to the first side, wherein the second redistribution layer includes a patterned metal layer having an interconnection circuit portion electrically connected to the die and a metal ring surrounding and insulated from the interconnection circuit portion. The through interlayer vias are located right under the metal ring and extending through the molded semiconductor device to be electrically connect the first redistribution layer and the second redistribution layer.