3D Semiconductor Package Structure for Warpage Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving reliable and large-scale electronic apparatus with advanced packaging techniques due to warpage issues in large-scaled electronic components, which affect miniaturization, speed, bandwidth, power consumption, and latency.
Innovation Solution
The development of a System on Integrate Chip (SoIC) package and method involving face-to-back bonding, chip-to-wafer bonding, and through-silicon vias to form a 3D packaging structure, using metal-to-metal and dielectric-to-dielectric bonding, and gap filling with dielectric materials to reduce warpage and enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If advanced packaging techniques with large-scaled semiconductor dies are used, then integration density and functionality are improved, but warpage issues occur affecting reliability
Solution Approach 1:
The package structure segments the semiconductor components into multiple separate dies (first semiconductor die, second semiconductor die, third semiconductor die) stacked in a 3D configuration. This segmentation allows each die to be optimized independently and reduces the overall warpage compared to a single large-scale die, while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent employs composite material structures including dielectric materials with fillers (such as tungsten oxide, barium titanate, or lead zirconate titanate) to create the insulating encapsulation and gap filling materials. These composite materials provide both mechanical support to reduce warpage and appropriate dielectric properties for electrical isolation, resolving the contradiction between integration density and warpage control.
2Quantity of substance
If 3D packaging structure with multiple stacked dies is implemented, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements preliminary action by forming through-silicon vias and conductive structures in the semiconductor dies before stacking them in the final 3D configuration. The insulating encapsulation is also applied to individual dies or intermediate structures prior to final assembly. This preliminary preparation simplifies the overall manufacturing process by breaking down complex 3D packaging into manageable sequential steps, reducing the actual assembly complexity while maintaining high integration density.
Data Source
AI summary
A package structure including a first semiconductor die, at least one second semiconductor die conductive terminals and an insulating encapsulation is provided. The at least one second semiconductor die is stacked on and electrically connected to the first semiconductor die. The conductive terminals are disposed on and electrically connected to the first semiconductor die. The insulating encapsulation laterally encapsulates the first semiconductor die, the at least one second semiconductor die and the conductive terminals, wherein the conductive terminals protrude from a surface of the insulating encapsulation. Furthermore, a method for forming the above-mentioned is also provided.