Semiconductor Package Warpage Reduction via Non-Planar Heat Spreader
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor packages face warpage issues due to temperature cycling and differences in thermal expansion properties of materials, limiting package size and thermal performance, which affects the mounting process and power consumption compliance.
Innovation Solution
The semiconductor package design includes a circuit board with a semiconductor chip, a spacer or stiffener, an encapsulant layer, and a heat spreading layer with specific thermal expansion coefficients and configurations to reduce warpage, such as a U-like shaped heat spreading layer or non-planar heat spreading layer, along with solder balls for mounting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If package size is increased, then power handling capability is improved, but warpage problem worsens
Solution Approach 1:
The package is divided into multiple functional layers including substrate, encapsulant, heat spreading layer, and stiffener. Each layer has specific thickness and material properties designed to manage thermal expansion independently, preventing overall package warpage while maintaining large size for power handling
Solution Approach 2:
The package uses composite structure with different materials (substrate, encapsulant, heat spreading layer, stiffener) having different thermal expansion coefficients. The stiffener with thermal expansion coefficient matching the substrate is specifically designed to counteract warpage forces while allowing large package footprint
2Temperature
If package size is increased, then thermal performance is improved, but manufacturing precision worsens
Solution Approach 1:
The thermal management function is segmented into heat spreading layer (immediate heat distribution) and stiffener (structural support). This segmentation allows the heat spreading layer to improve thermal performance across large areas while the stiffener maintains manufacturing precision by preventing substrate deformation
Solution Approach 2:
The stiffener's thermal expansion coefficient is specifically selected to match the substrate, creating a parameter match that prevents differential thermal expansion. This parameter optimization allows large package sizes to maintain flatness during manufacturing and operation
3Power
If power consumption is increased, then functionality is improved, but thermal performance worsens
Solution Approach 1:
The heat spreading layer acts as an intermediary between the high-power semiconductor chip and the environment. It mediates thermal energy distribution, spreading heat from concentrated chip sources across the entire package area, enabling high power consumption while maintaining acceptable thermal performance
Solution Approach 2:
The phase change material in the heat spreading layer absorbs excess thermal energy through phase transition (solid-liquid transformation). This phase change mechanism provides passive thermal management, allowing the system to handle high power consumption without proportional temperature increase
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively reduces warpage and enhances thermal performance, allowing for larger package sizes and improved power handling while ensuring reliable mounting and functionality.
Implementation Method 1
a heat spreading layer, formed over the encapsulant layer and the spacer
Implementation Method 2
differences in the thermal expansion properties of the various materials of the package, e.g., differences in the thermal expansion properties of the substrate and encapsulating material
Data Source
AI summary
A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.