Semiconductor Package Vertical Interconnects via Wire Thinning
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in reducing volume and weight while increasing integration, with 3D stacking methods like package-on-package (PoP) structures seeking cost-effective vertical connection solutions that simplify manufacturing processes.
Innovation Solution
A package structure utilizing wire bonding to create conductive wire segments for vertical connections between semiconductor dies and redistribution layers, replacing traditional copper pillars or through insulator vias, with a method involving redistribution layers, insulating encapsulants, and thinning processes to form conductive wire segments that connect semiconductor dies to redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional copper pillars or through insulator vias are used for vertical connections, then manufacturing precision and reliability are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and removes the complex copper pillar or through insulator via structures from the package design, replacing them with simpler wire bonding connections. This extraction eliminates the need for precise via formation, copper deposition, and complex alignment processes, thereby reducing manufacturing complexity while maintaining electrical connectivity between packages.
Solution Approach 2:
The patent employs wire bonding as a simpler, more cost-effective alternative to expensive copper pillars and through insulator vias. Wire bonding uses readily available materials and established processes that are less costly and simpler to implement, achieving the same functional goal of vertical electrical connection without the complexity of metal deposition and via formation.
2Quantity of substance
If 3D stacking technologies are implemented, then packaging density is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the vertical connection function into separate wire bonding operations rather than requiring integrated copper pillar or via structures. This segmentation allows each package layer to be connected independently through wires, simplifying the manufacturing process while achieving high packaging density through 3D stacking of multiple packages.
3Ease of manufacture
If wire bonding is used for vertical connections, then manufacturing cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The wire bonding process utilizes the natural properties of the wire and bonding materials to achieve self-alignment and self-connection. The wire bonding equipment automatically positions and bonds wires between contact pads, leveraging the self-service capability of the bonding process to achieve precise connections without requiring extremely tight tolerances on package substrate alignment, thereby reducing overall manufacturing precision requirements.
Data Source
AI summary
A method of fabricating a package structure including at least the following steps is provided. A carrier is provided. A first package is formed on the carrier. The first package is formed by at least the following steps. A first redistribution layer is formed on the carrier, wherein the first redistribution layer has a first surface and a second surface opposite to the first surface. A semiconductor die is bonded on the first surface of the first redistribution layer. The semiconductor die is electrically connected to the first redistribution layer through a plurality of conductive wires. An insulating material is formed to encapsulate the semiconductor die and the plurality of conductive wires. A thinning process is performed to obtain an insulating encapsulant by reducing a thickness of the insulating material until a portion of each of the conductive wires is removed to form a plurality of conductive wire segments, wherein the semiconductor die is electrically insulated from the first redistribution layer after the thinning process. A second redistribution layer is formed on a top surface of the insulating encapsulant, and over the semiconductor die. The second redistribution layer is electrically connected to the first redistribution layer and to the semiconductor die by the plurality of conductive wire segments.