Semiconductor Package Wiring Structural Body Eliminating Warping
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Solution Overview
Problem
Conventional semiconductor packages face issues with connecting reliability due to thermal expansion differences between semiconductor chips and multi-layer wiring boards, leading to warping and void generation, as well as potential insulation failures from residual flux.
Innovation Solution
A manufacturing method involving a semi-cured insulation layer formed on a supporting body, with photolithography to create openings for electrode alignment, followed by sealing resin application and removal of the supporting body, allowing direct electrical connection between the semiconductor chip and wiring structural body without solder bumps, thus reducing thermal expansion issues and voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder bumps are used to connect the semiconductor chip to the multi-layer wiring board, then electrical connection is achieved, but thermal expansion differences cause warping and reduce connecting reliability
Solution Approach 1:
The patent removes the multi-layer wiring board from the package structure, eliminating the thermal expansion mismatch problem between the wiring board and semiconductor chip. The semiconductor chip is directly mounted on the substrate without intermediate wiring layers, thereby preventing warping caused by differential thermal expansion while maintaining electrical connection functionality.
Solution Approach 2:
Instead of mounting the semiconductor chip on the multi-layer wiring board as in conventional structures, the patent inverts the mounting relationship by directly connecting the chip electrodes to the substrate. This inversion eliminates the problematic intermediate wiring board layer that causes thermal expansion issues.
2Reliability
If underfill resin is supplied between the semiconductor chip and multi-layer wiring board, then sealing is achieved, but voids are generated reducing package quality
Solution Approach 1:
The patent eliminates the multi-layer wiring board that necessitates underfill resin application. By directly mounting the semiconductor chip on the substrate without intermediate wiring layers, the need for underfill resin is removed, thereby preventing void generation and improving package quality.
3Ease of manufacture
If flux is applied during soldering process, then soldering is facilitated, but residual flux causes insulation failures
Solution Approach 1:
The patent removes the soldering process entirely by eliminating the multi-layer wiring board and its associated solder bumps. Direct electrode mounting is performed without flux, thereby preventing residual flux from causing insulation failures while maintaining manufacturing feasibility.
4Reliability
If multiple layers are stacked to form the multi-layer wiring board, then electrical connectivity is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the complex multi-layer wiring board structure, retaining only the essential substrate. Electrical connection is achieved through direct electrode mounting on the substrate without requiring multiple stacked wiring layers, thereby simplifying the overall device structure while maintaining connectivity.
Solution Approach 2:
The patent separates the wiring board functionality from the substrate, eliminating the need for complex multi-layer stacking. The substrate alone serves as the mounting platform, with electrical connections established through direct electrode contact rather than through multiple intermediate wiring layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances connecting reliability by eliminating thermal expansion-induced warping and voids, while preventing insulation failures from flux residues, resulting in improved electrical connections and package integrity.
Implementation Method 1
a first step of forming a semi-cured insulation layer made of a photosensitive material; a second step of forming an opening part in the insulation layer by a photolithography method
Data Source
AI summary
A manufacturing method includes forming a semi-cured insulation layer made of a photosensitive material on a supporting body; forming an opening part in the insulation layer by a photolithography method, the opening part being configured to expose the supporting body; arranging a semiconductor chip on the insulation layer so that a position of an electrode of the semiconductor chip is consistent with a position of the opening part, and curing the insulation layer; forming sealing resin on a surface of the insulation layer at the semiconductor chip side, the sealing resin being configured to seal the semiconductor chip; removing the supporting body; and providing a wiring layer on a surface of the insulation layer opposite to the semiconductor chip side, the wiring layer being electrically connected to the electrode exposed in the opening part, so that a wiring structural body including the insulation layer and the wiring layer is formed.