Semiconductor Packaging Arrangement with Intermediary Conductive Member
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor packaging arrangements face challenges in optimizing the spacing and electrical coupling of transistor devices, particularly high-voltage devices, which affect switching efficiency and avalanche voltage performance due to parasitic inductance and height differences in package outlines.
Innovation Solution
The use of conductive members with varying melting points and structures, such as ball bumps and bond wire loops, to space and electrically couple source and gate electrodes to die pads and leads, ensuring proper spacing and mechanical integrity while minimizing parasitic inductance and accommodating height differences in standard packages like SuperSO8 and TO220.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate electrode is spaced far from the lead to reduce parasitic inductance, then switching efficiency is improved, but mechanical integrity and electrical coupling deteriorate
Solution Approach 1:
A conductive member serves as an intermediary between the gate electrode and the lead, providing both mechanical support and electrical connection. This intermediary enables the gate electrode to be positioned at an optimal distance from the lead for reduced parasitic inductance while maintaining mechanical integrity through the physical connection provided by the conductive member.
2Ease of manufacture
If standard package outlines are used with fixed height requirements, then manufacturing compatibility is improved, but the ability to optimize spacing for high-voltage device performance deteriorates
Solution Approach 1:
The conductive member acts as an adaptable intermediary that can be positioned at varying heights within standard package outlines. This enables compatibility with existing manufacturing processes while providing the flexibility to optimize the spacing between electrodes and substrates for enhanced high-voltage device performance.
Solution Approach 2:
The height and positioning of conductive members are optimized as adjustable parameters. By varying these parameters within the constraints of standard package outlines, the patent maintains manufacturing compatibility while achieving optimized spacing for improved high-voltage device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances switching efficiency by reducing parasitic inductance and allows for tailored avalanche voltage performance, improving the mounting and performance of high-voltage transistor devices in standard semiconductor packages.
Implementation Method 1
parasitic inductance and height differences in package outlines
Implementation Method 2
conductive members with varying melting points and structures
Data Source
AI summary
A semiconductor packaging arrangement includes a transistor device including a first side including a source electrode and a gate electrode, a die pad having a first surface, and a lead having a first surface. A first conductive member is arranged between the source electrode and the first surface of the die pad and spaces the source electrode from the first surface of the die pad by a distance that is greater than a distance between the gate electrode and the first surface of the lead.