Semiconductor Pad Array Via-In-Pad Configuration
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Solution Overview
Problem
Existing semiconductor device pads formed by different methods exhibit varying reliability issues, such as reduced adhesion, poor mechanical performance, stress concentration, and poor reliability in temperature cycling, leading to overall low reliability and functional performance.
Innovation Solution
The use of a combination of via-in-pad (VIP) and non-via-in-pad (NVIP) configurations on the substrate, where VIP pads directly contact conductive vias and NVIP pads do not, to enhance package density and reliability by offsetting the disadvantages of each type, with NVIP pads being more resistant to stress and VIP pads providing high-density connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If via-in-pad (VIP) configuration is used to increase connection density, then package density is improved, but stress concentration and reliability under temperature cycling and drop tests deteriorate
Solution Approach 1:
The patent applies local quality by differentiating pad structures based on their functional requirements. VIP pads are used in specific locations where high connection density is critical, while NVIP pads are used in locations where stress resistance is more important. This localized differentiation allows each pad type to optimize its performance for its specific role in the package.
Solution Approach 2:
The patent segments the pad array into two distinct types: VIP pads and NVIP pads. This segmentation allows the system to distribute different pad configurations across the substrate, with VIP pads providing high-density connections in certain areas and NVIP pads providing stress-resistant connections in other areas, thereby resolving the contradiction between density and reliability.
2Reliability
If non-via-in-pad (NVIP) configuration is used to reduce stress concentration, then reliability under temperature cycling and drop tests is improved, but package density deteriorates
Solution Approach 1:
The patent applies local quality by strategically placing NVIP pads in locations where stress resistance is prioritized, such as areas prone to thermal expansion stress or mechanical impact. This localized application ensures that NVIP pads provide stress relief where needed without compromising overall package density through universal application.
Solution Approach 2:
The patent segments the pad array into two distinct types: VIP pads and NVIP pads. This segmentation allows the system to distribute different pad configurations across the substrate, with NVIP pads providing stress-resistant connections in specific areas while VIP pads handle density-critical areas, thereby resolving the contradiction between reliability and density.
3Ease of manufacture
If pads are formed by conventional methods to ensure manufacturing simplicity, then ease of manufacture is improved, but adhesion and mechanical performance deteriorate
Solution Approach 1:
The patent applies parameter changes by modifying the structural parameters of the pads rather than changing the manufacturing process parameters. By altering the pad configuration from uniform to differentiated (VIP vs. NVIP), the patent achieves improved adhesion and mechanical performance through structural optimization while maintaining compatibility with conventional manufacturing methods.
Data Source
AI summary
A semiconductor device includes a first substrate including a surface, and a pad array on the surface of the substrate, wherein the pad array comprises a first type pad and a second type pad located on a same level. The semiconductor device further includes a conductive bump connecting either the first type pad or the second type pad to a second substrate and a via connected a conductive feature at a different level to the first type pad and the via located within a projection area of the first type pad and directly contacting the first type pad. The semiconductor device also has a dielectric in the substrate and directly contacting the second type pad, wherein the second type pad is floated on the dielectric.