Semiconductor Pad Patterns Bridge Bit Line and Page Buffer Pitch Mismatch
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Solution Overview
Problem
In semiconductor devices, particularly NAND flash memory, connecting bit line patterns and page buffer patterns with different pitches is challenging due to the limitations of double patterning technology (DPT), which complicates the formation of contacts between patterns with varying lengths and layers.
Innovation Solution
The semiconductor device incorporates pad patterns with a greater pitch than bit line patterns, allowing for connections via contacts, and page buffer patterns with a pitch greater than bit line patterns, formed on different or the same layers, using a layout method that involves forming bit line patterns, pad patterns, and page buffer patterns with specific connections and contacts to facilitate inter-layer connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technology is used to form bit line patterns, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the formation of bit line patterns into multiple stages through double patterning technology. First, a mandrel pattern is formed, then removed after transferring the pattern to the bit line structure. This segmentation allows precise pitch control while managing the complexity of the overall process through systematic breakdown of steps.
Solution Approach 2:
The patent employs preliminary action by forming mandrel patterns before the actual bit line patterns. The mandrels serve as temporary structures that define the pitch and positioning of bit lines in advance. This preliminary structuring enables subsequent removal of mandrels after their pattern-transfer function is fulfilled, achieving precision without permanently complicating the final device structure.
2Adaptability or versatility
If bit line patterns and page buffer patterns with different pitches are connected, then adaptability is improved, but manufacturing precision deteriorates
Solution Approach 1:
The patent introduces pad patterns as intermediary elements between bit line patterns and page buffer patterns. These pad patterns serve as mediator structures that bridge the pitch difference between the two pattern systems. By connecting bit lines to pads and pads to page buffers, the intermediary pad layer enables adaptability between different pitches while maintaining manufacturing precision through controlled alignment at each interface.
3Adaptability or versatility
If contacts are formed on pad patterns to connect different layers, then adaptability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing pad patterns that serve multiple functions: they act as connection points for bit lines, serve as alignment references for contact formation, and provide interfaces to page buffer patterns. This multi-functionality reduces the need for separate dedicated structures for each function, thereby improving adaptability while managing device complexity through consolidated design elements.
Data Source
AI summary
Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).