Semiconductor Package Pad Layout for Adhesive-Free Direct Bonding
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Solution Overview
Problem
Existing semiconductor packages face challenges in achieving high-quality bonding interfaces and surface topology characteristics due to the limitations of adhesive films and connection bumps, which hinder the integration of more components and miniaturization.
Innovation Solution
A semiconductor chip design with varying pad sizes and wiring patterns on the bonding surface, allowing direct bonding without adhesives, by optimizing the surface topology through controlled area ratios and distribution of top wiring patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If top wiring patterns have uniform occupied area between all pads, then manufacturing process is simple, but surface topology characteristics are poor and bonding interface quality is reduced
Solution Approach 1:
The patent applies local quality by varying the occupied area of top wiring patterns between different groups of pads. Specifically, first top wiring patterns have a first occupied area between first pads, while second top wiring patterns have a second occupied area that is larger than the first occupied area between second pads. This localized variation in wiring pattern dimensions optimizes surface topology characteristics at different regions of the bonding surface, improving adhesion and alignment for direct bonding applications.
2Adaptability or versatility
If adhesive films or connection bumps are used for bonding, then bonding strength is sufficient, but the package structure becomes more complex and component integration is limited
Solution Approach 1:
The patent extracts and eliminates adhesive films and connection bumps from the bonding structure by implementing direct bonding between semiconductor chips. The improved surface topology characteristics achieved through varied top wiring pattern occupied areas enable sufficient bonding strength without requiring additional bonding materials or structures, thereby simplifying the overall package structure and increasing component integration capacity.
Solution Approach 2:
Instead of using additional materials (adhesive films) or structures (connection bumps) to achieve bonding, the patent inverts the approach by optimizing the wiring pattern geometry itself to create the bonding interface. The varied occupied areas of top wiring patterns directly form the bonding surface topology, eliminating the need for separate bonding components.
3Strength
If pad sizes are made larger to improve bonding area, then bonding strength increases, but the available space for other components and wiring reduces
Solution Approach 1:
The patent applies local quality by making pad sizes and wiring pattern occupied areas location-dependent. Different groups of pads have different occupied areas in their respective regions, allowing optimization of bonding strength at each location based on local requirements while maintaining overall space efficiency on the chip surface.
Solution Approach 2:
The patent changes the parameter of wiring pattern occupied area to optimize bonding characteristics. By varying the occupied area parameter across different regions, the patent achieves improved surface topology and bonding strength without uniformly increasing pad sizes, thereby preserving available space for other components and wiring.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads. The plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface. On a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from a top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads. From a top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than a second area.