Semiconductor Pad Plated Layer Thickness and Area Optimization
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Solution Overview
Problem
The reliability of semiconductor devices with bonding pads is compromised due to issues such as cracking during wire bonding and warpage of the semiconductor substrate, primarily caused by the stress and physical impact on the plated layers, which affects the manufacturing yield and performance.
Innovation Solution
The semiconductor device design includes a configuration where the area of the opening portion for the gate pad is smaller than that of the source pad, and the thickness of the plated layer over the gate pad is greater than that over the source pad, enhancing durability against physical impact and reducing stress-related warpage, thereby improving reliability and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the plated layer thickness is increased to improve durability against physical impact, then the reliability improves, but the stress on the semiconductor substrate increases causing warpage
Solution Approach 1:
The patent applies different plated layer thicknesses to different regions: the first plated layer over the source pad has a first thickness, while the second plated layer over the gate pad has a second thickness that is greater than the first thickness. This local differentiation allows the gate pad region (which experiences more stress during wire bonding) to have enhanced durability, while the overall substrate stress is optimized by not uniformly increasing thickness across all pads.
2Stability of the object's composition
If the opening portion area is decreased to reduce stress and warpage, then the substrate stability improves, but the bonding pad effectiveness may be compromised
Solution Approach 1:
The patent creates different opening portion areas for different pads: the first opening portion for the source pad has a first area, while the second opening portion for the gate pad has a second area that is smaller than the first area. This local differentiation reduces stress and warpage in the gate pad region (which is more sensitive to stress), while the source pad maintains a larger area for effective bonding, thus resolving the contradiction between substrate stability and bonding effectiveness.
3Reliability
If the plated layer thickness is increased to reduce cracking during wire bonding, then the reliability improves, but the manufacturing complexity increases
Solution Approach 1:
The patent specifies that the second plated layer over the gate pad has a greater thickness than the first plated layer over the source pad. This localized thickness differentiation targets the specific region (gate pad) that is more prone to cracking during wire bonding, rather than uniformly increasing thickness across all pads. This approach improves reliability where needed while minimizing the overall manufacturing complexity and material usage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the likelihood of cracking during wire bonding and warpage of the semiconductor substrate, enhancing the overall reliability and manufacturing yield of the semiconductor device by optimizing the plated layer thickness and area ratios.
Implementation Method 1
a first plated layer formed over the portion of the first conductive film pattern exposed in the first opening portion; and a second plated layer formed over the portion of the second conductive film pattern exposed in the second opening portion
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming an interlayer insulating film over a main surface of a semiconductor substrate, forming a first conductive film pattern for a first pad and a second conductive film pattern for a second pad over the interlayer insulating film, forming an insulating film over the interlayer insulating film such that the insulating film covers the first and the second conductive film patterns, forming a first opening portion for the first pad, the first opening portion exposing a portion of the first conductive film pattern, and a second opening portion for the second pad, the second opening portion exposing a portion of the second conductive film pattern, in the insulating film, and forming a first plated layer by plating over the portion of the first conductive film pattern exposed in the first opening portion, and a second plated layer.