Semiconductor Pad Segmentation for Probe Mark Isolation
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Solution Overview
Problem
The reduction in semiconductor device size and pitch leads to larger probe marks during the probe test, which reduces the contact area between wires and pads, causing poor coupling and potential signal delay due to increased resistance and pore formation at the interface between the pad and rewiring layer.
Innovation Solution
A manufacturing method involving the formation of a semiconductor device with distinct probe and coupling regions, where the probe needle contacts only the probe region, and a conductive film is used to cover the coupling region, preventing probe mark-related issues and ensuring a pore-free rewiring layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the pad size is reduced to increase pin count, then the device functionality is improved, but the probe mark becomes larger relative to the pad, reducing contact area and causing poor coupling
Solution Approach 1:
The pad is divided into two distinct regions: a probe region for electrical testing and a coupling region for wire bonding. This segmentation allows the probe mark to be confined to one region while preserving the other region for high-quality electrical coupling, thus resolving the contradiction between maintaining small pad size for high pin count and ensuring sufficient contact area for reliable coupling.
Solution Approach 2:
Different regions of the pad are assigned different functions with different quality requirements. The probe region accepts the probe mark as its intended function, while the coupling region maintains high surface quality for optimal wire bonding. This local differentiation allows the pad to simultaneously satisfy both the need for small overall size and the need for high-quality contact area.
2Measurement precision
If the probe needle contacts the pad for testing, then electrical properties are measured, but probe marks are formed that increase resistance and cause signal delay
Solution Approach 1:
By segmenting the pad into probe and coupling regions, the measurement function and signal transmission function are separated spatially. The probe needle contacts only the probe region for electrical testing, while the coupling region remains probe-free to ensure low-resistance, high-reliability signal transmission for wire bonding.
Solution Approach 2:
The probe region acts as an intermediary that absorbs the harmful effect of the probe mark. By designing this region specifically to accommodate probe contact, the harmful effects are localized and do not propagate to the coupling region, thus protecting signal transmission quality.
3Ease of manufacture
If plating is performed over the entire pad including probe mark regions, then complete coverage is achieved, but pores form at the interface between pad and rewiring layer
Solution Approach 1:
The plating process is applied selectively to different regions. The coupling region receives complete plating coverage for robust rewiring layer formation, while the probe region is either excluded from plating or receives reduced plating to avoid pore formation at the pad interface. This selective plating strategy maintains interface flatness while achieving necessary coverage.
Solution Approach 2:
Different plating qualities are applied to different regions. The coupling region receives high-quality, pore-free plating for reliable electrical connection, while the probe region accepts lower-quality or no plating since it is not used for final electrical coupling. This local quality differentiation resolves the contradiction between complete coverage and interface flatness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables size reduction, high pin count, improved electrical properties, and enhanced reliability of semiconductor devices by eliminating probe mark-induced pores and ensuring a flat interface for better contact and signal transmission.
Implementation Method 1
it inevitably gives an external damage, as a probe mark, to the surface of a pad
Implementation Method 2
forming a conductive film covering therewith the first insulating film and the coupling region over the pad
Data Source
AI summary
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.