Stacked Semiconductor Pads with Sacrificial Layer Recess Bonding
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Solution Overview
Problem
Current semiconductor packaging techniques face challenges in achieving high-density stacked structures with improved electrical performance and driving stability, particularly in vertically stacked semiconductor devices, where uneven surfaces and intervening components can lead to gaps and reduced connectivity.
Innovation Solution
The proposed solution involves a semiconductor device design where each chip includes a sacrificial layer with polishing selectivity, allowing for precise stacking and bonding, with a method that includes forming upper and lower insulating layers and bonding layers on substrates, and applying a polishing process to create flat surfaces for improved contact and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertically stacked semiconductor devices are constructed to achieve high density, then the footprint area is reduced, but uneven surfaces and intervening components create gaps that reduce electrical connectivity
Solution Approach 1:
The patent applies preliminary planarization by forming sacrificial layers on chip surfaces before stacking. These sacrificial layers are removed after bonding to create recesses that accommodate bonding wire loops, ensuring flat bonding surfaces and eliminating gaps that would compromise electrical connectivity in high-density vertical stacks.
Solution Approach 2:
The patent introduces bonding wire loops as intermediary elements between bonding pads on stacked chips. These wire loops serve as flexible connectors that bridge the bonding interfaces, maintaining reliable electrical connectivity despite the presence of intervening components and ensuring stable connections in vertically stacked configurations.
2Reliability
If bonding wire loops are used to connect stacked chips, then electrical connectivity is maintained, but the bonding process becomes complex and time-consuming
Solution Approach 1:
The patent performs preliminary formation of sacrificial layers and recesses on chip surfaces before the bonding process. This advance preparation simplifies the subsequent bonding operation by pre-defining the exact geometry needed to accommodate wire loops, reducing the complexity and time required during the actual bonding step.
Solution Approach 2:
The sacrificial layers automatically define the recess geometry needed for wire loop accommodation through the planarization process. The structure self-organizes to create the appropriate bonding interface geometry, eliminating the need for complex external patterning or alignment processes during bonding.
3Ease of manufacture
If conventional packaging techniques are used for stacked devices, then manufacturing is simpler, but electrical performance and driving stability are reduced
Solution Approach 1:
The patent applies preliminary planarization and sacrificial layer formation to create optimized bonding surfaces before stacking. This advance preparation enables improved electrical performance through better contact and connectivity while maintaining manufacturing feasibility by using standard semiconductor fabrication processes.
Solution Approach 2:
The patent applies local planarization and recess formation only at the bonding interfaces where wire loops need to be accommodated. This localized approach improves electrical performance at critical bonding points without requiring complete redesign of the entire manufacturing process, maintaining ease of manufacture while enhancing electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical performance and driving stability by ensuring consistent and reliable contact between stacked chips, reducing processing time, and improving productivity through intermittent polishing and precise layer arrangements.
Implementation Method 1
applying a polishing process to the at least one preliminary second chip to remove at least a portion of the second sacrificial layer and to form at least one second chip
Data Source
AI summary
A semiconductor device includes a first chip and a second chip stacked on the first chip. The first chip includes a first substrate, a first upper pad on an upper surface of the first substrate, a first upper insulating layer surrounding a lower portion of the first upper pad and a sacrificial layer surrounding an upper portion of the first upper pad. The second chip includes a second substrate, a second upper pad on an upper surface of the second substrate and a second upper insulating layer surrounding the second upper pad, wherein a thickness of the second upper pad is less than a thickness of the first upper pad.