Semiconductor Package Pad Stack for Reliable Bump Connection
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved electrical properties and increased reliability due to limitations in the design and fabrication processes, particularly in the integration of semiconductor chips and dielectric structures.
Innovation Solution
The semiconductor package design incorporates a first dielectric structure with a first pad and a second dielectric structure, featuring a bump electrically connected to the first pad, where the first pad comprises a first conductive layer and a second conductive layer, with the bump positioned closer to the first conductive layer than the second conductive layer, and includes key patterns and gap-fill layers for enhanced alignment and bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-layer pad structure is used, then the manufacturing process is simple, but the electrical connectivity and reliability are insufficient
Solution Approach 1:
The pad structure is divided into multiple conductive layers (first conductive layer and second conductive layer) stacked vertically. This segmentation allows each layer to serve specific functions: the first conductive layer provides primary electrical connection to the bump, while the second conductive layer enhances connectivity to the chip pad. The multi-layer segmentation resolves the contradiction by improving electrical reliability without requiring complex lateral expansions.
Solution Approach 2:
The invention transitions from a conventional single-layer planar pad structure to a multi-layer vertical stack structure. By adding the vertical dimension with stacked conductive layers, the pad achieves improved electrical connectivity in the Z-direction while maintaining a compact footprint in the XY-plane. This dimensional transition resolves the contradiction between reliability improvement and structural complexity.
2Reliability
If the bump is positioned equidistant from both conductive layers, then the structure is symmetric and simple, but the electrical performance is suboptimal
Solution Approach 1:
The bump position is deliberately offset closer to the first conductive layer rather than being equidistant from both layers. This local quality adjustment optimizes the electrical connection path: the shorter distance to the first conductive layer reduces parasitic inductance and resistance, while the second conductive layer provides additional connectivity pathways. This asymmetric positioning resolves the contradiction by prioritizing electrical performance over symmetric simplicity.
3Reliability
If the top surface area of the first conductive layer is large, then the electrical connection area is increased, but the area available for other components is reduced
Solution Approach 1:
The conductive connection area is expanded vertically through multiple stacked layers rather than laterally through a larger single-layer area. The first and second conductive layers provide cumulative connection area in the vertical dimension, maintaining a compact horizontal footprint. This resolves the contradiction by achieving large effective connection area without consuming excessive planar space that would be unavailable for other components.
Solution Approach 2:
The pad structure uses composite conductive layers with different geometries and positions. The first conductive layer has a specific top surface area optimized for bump connection, while the second conductive layer provides additional connection area at a different vertical level. This composite structure achieves total connection area expansion without requiring any single layer to be excessively large, preserving space for other components.
Data Source
AI summary
A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip provided on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be provided between the bump and the first chip of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than to the second conductive layer.