Semiconductor Source and Drain Pad Layout for Parasitic Capacitance Reduction
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Solution Overview
Problem
Field effect transistors face challenges in minimizing electrical interference and optimizing bonding areas as they shrink in size, requiring effective placement and design of source and drain pads to maintain adequate bonding while reducing parasitic capacitance.
Innovation Solution
The semiconductor device incorporates a design with source and drain pads that overlap partially with the active layer, featuring via holes and plugs to reduce resistance and parasitic capacitance, with the pads' resistance per unit length being lower than the electrodes', and a gate dielectric layer to enhance current flow and area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the source pad and drain pad are placed with large bonding areas to facilitate external circuit bonding, then the bonding area is improved, but the electrical interference and parasitic capacitance on the field effect transistor increases
Solution Approach 1:
The source pad and drain pad are positioned to overlap with the drain region and source region respectively in the planar view, utilizing the vertical dimension for electrical connection through via holes. This dimensional arrangement allows the pads to be placed within the active area without increasing the footprint, thereby maintaining large bonding areas while reducing the horizontal separation distance that would cause electrical interference.
Solution Approach 2:
Via holes filled with conductive material serve as intermediaries to connect the source pad to the source electrode and the drain pad to the drain electrode. This intermediary structure allows electrical connection while physically separating the pads from the electrodes, reducing direct parasitic capacitance between the pads and the active channel.
2Area of stationary object
If the source pad and drain pad are placed with large bonding areas to facilitate external circuit bonding, then the bonding area is improved, but the device size increases
Solution Approach 1:
The source pad and drain pad regions are merged with the active area by allowing their orthogonal projections to overlap with the drain region and source region respectively. This merging eliminates the need for separate pad areas outside the active region, thereby providing large bonding areas without increasing the overall device footprint.
Solution Approach 2:
The electrical connection is achieved through the vertical dimension using via holes that pass through the insulating layer, allowing the pads to be positioned in the planar view without increasing the device's horizontal or vertical dimensions. This enables large bonding areas to be integrated within the existing device footprint.
3Area of moving object
If the pads are positioned to overlap with the active region, then the device size is reduced, but the parasitic capacitance between pads and electrodes increases
Solution Approach 1:
The via holes filled with conductive material act as intermediaries between the pads and the electrodes. Although the pads overlap with the active region in planar view, the via holes provide a vertical connection path that isolates the pads from direct lateral electric field interaction with the electrodes, thereby reducing parasitic capacitance while maintaining compact device size.
Solution Approach 2:
The electrical connection path is segmented into multiple stages: the pad in the upper layer, the via hole connecting through the insulating layer, and the electrode in the lower layer. This segmentation separates the pad and electrode in the vertical dimension, reducing the overlapping area effect and thereby minimizing parasitic capacitance despite the planar overlap.
Data Source
AI summary
A semiconductor device includes an active layer, at least one source electrode, at least one drain electrode, at least one gate electrode, a first insulating layer, a first source pad, a first drain pad, at least one source plug, and at least one drain plug. The source electrode and the drain electrode are both disposed on the active layer. Projections of the source electrode and the drain electrode on the active layer form a source region and a drain region, respectively. The first source pad and the first drain pad are both disposed on the first insulating layer. A projection of the first source pad on the active layer forms a source pad region. An area of an overlapping region between the source pad region and the drain region is smaller than or equal to 40% of an area of the drain region.