Semiconductor Pad Wiring MIM Capacitor Integration

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Solution Overview

Problem

The presence of a ring pattern in the insulating layer surrounding the pad in semiconductor devices can lead to deteriorated power and signal integrity by obstructing wiring configurations, which existing technologies have not effectively addressed.

Innovation Solution

The semiconductor device incorporates a configuration where first, second, and third wirings are positioned between the pad and circuit, with power supplies providing different voltages to form metal-insulator-metal (MIM) capacitors, and a pad contact directly connects the pad to the circuit, eliminating the ring pattern and enhancing wiring efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a ring pattern is formed in the insulating layer below the pad, then the pad structure is defined, but the wiring cannot be arranged in the surrounded portion leading to deteriorated power and signal integrity

Engineering Contradiction:
Improvepower and signal integrityVSAvoidwiring arrangement complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The insulating layer is segmented into multiple regions: a first region with the ring pattern that defines the pad structure, and a second region without the ring pattern that allows wiring arrangement. This segmentation resolves the contradiction by allowing both pad definition and wiring placement in different spatial zones.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The wiring is arranged in a dimension outside the ring pattern's enclosed area. Instead of trying to fit wiring within the ring pattern's inner space, the solution extends the wiring path to the outer region of the insulating layer, utilizing additional spatial dimensionality to achieve both pad definition and wiring connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If multiple wirings are arranged between the pad and circuit, then wiring flexibility is improved, but the device size increases

Engineering Contradiction:
Improvewiring configuration flexibilityVSAvoiddevice area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Multiple wirings (first, second, and third wirings) are merged into a compact stacked arrangement between the pad and circuit. Instead of spreading them out horizontally, they are vertically integrated in a confined space, achieving wiring flexibility without proportionally increasing the device footprint.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The multiple wirings are nested within each other in a hierarchical structure, with the first wiring closest to the pad, followed by the second wiring, and the third wiring closest to the circuit. This nested arrangement allows multiple connection paths to coexist in a compact volume, providing flexibility without excessive area occupation.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration increases power and signal integrity by removing the ring pattern, allowing for improved electrical connections and reduced size, while the MIM capacitors enhance performance, resulting in a semiconductor device with increased reliability and efficiency.

Implementation Method 1

The first and second power supplies may supply different powers to adjacent metals included in the first to third wirings to form a metal-insulator-metal (MIM) capacitor

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The third power supply is configured to supply a different power to the first wiring and the second wiring, or the second wiring and the third wiring

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS10748846B2Semiconductor device
Publication Date: 2020.08.18 SAMSUNG ELECTRONICS CO LTD
  • US10748846B2 patent drawing
  • US10748846B2 patent drawing
  • US10748846B2 patent drawing

AI summary

A semiconductor device may include an insulating layer, a pad, a circuit, at least one first wiring, at least one second wiring, at least one third wiring, and a pad contact. The pad may be disposed on the insulating layer. The circuit may be disposed in the insulating layer. The circuit may be positioned below the pad. The first wiring may be disposed between the pad and the circuit. The second wiring may be disposed between the pad and the first wiring. The third wiring may be disposed between the pad and the second wiring. The pad contact may be configured to directly connect the pad to the circuit.