Semiconductor Parallel Test Data Circuits for Even-Odd Pattern Matching
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Solution Overview
Problem
Existing semiconductor devices face challenges in efficiently performing parallel tests to verify data stored in core cells by ensuring accurate pattern matching during write and read operations.
Innovation Solution
The semiconductor device incorporates even and odd data input circuits that store data with specific patterns in response to strobe signals, along with a comparison code generation circuit to verify data integrity during parallel tests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in core cells using sequential write operations, then data integrity can be verified, but testing time increases significantly
Solution Approach 1:
The patent divides the testing process into separate even and odd data input circuits that operate in parallel. Each circuit handles specific data patterns (even or odd) independently, allowing simultaneous write operations to different core cells without interference, thus reducing total testing time while maintaining verification reliability
Solution Approach 2:
The patent uses input strobe signals to pre-synchronize data before it is written to core cells. By controlling the timing and sequence of data input through strobe signals, the system ensures proper data alignment and readiness before parallel write operations begin, enabling efficient simultaneous testing without compromising data integrity
2Productivity
If parallel write operations are performed to multiple core cells simultaneously, then testing efficiency improves, but data pattern accuracy may deteriorate
Solution Approach 1:
The patent assigns different data patterns (even/odd) to different input circuits and core cells. Each circuit is specialized for its specific pattern type, ensuring that data written to even core cells has even patterns while odd core cells receive odd patterns. This localized specialization maintains pattern accuracy while enabling parallel operations
Solution Approach 2:
The patent dynamically controls the selection and timing of data patterns through input strobe signals. The system can flexibly switch between even and odd data patterns based on testing requirements, allowing adaptive parallel write operations that maintain accuracy regardless of which core cells are being tested simultaneously
3Productivity
If separate data input circuits are used for even and odd core cells, then parallel testing capability is enhanced, but device complexity increases
Solution Approach 1:
The patent designs the even and odd data input circuits using identical structural components and logic, where each circuit can handle both data input and pattern generation functions. This universal design allows the same circuit architecture to be replicated for different purposes (even/odd handling), reducing overall system complexity through standardization while maintaining parallel testing capability
Solution Approach 2:
The patent creates a replicated copy of the data input circuit architecture for even and odd core cells. By copying the proven working design rather than creating entirely new circuits, the system achieves parallel functionality with minimal additional complexity, as the copied circuits inherit the reliability and simplicity of the original design
Data Source
AI summary
According to an embodiment of the present disclosure, a semiconductor device includes an even data input circuit configured to store, in an even core cell, data that is input through an even data pad and that has a first pattern in response to an even data input strobe signal in a write operation of a parallel test. The semiconductor device includes an odd data input circuit configured to store, in an odd core cell, data that is input through the even data pad and that has a second pattern in response to an odd data input strobe signal in the write operation of the parallel test.