Semiconductor Component Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor components miniaturize, their parasitic capacitance increases, necessitating a manufacturing process to address this issue.
Innovation Solution
A method involving a series of deposition and etching steps on a semiconductor substrate, including the formation of oxide and polysilicon layers, trench creation, and metal layer deposition, aimed at reducing parasitic capacitance and component volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the structure of semiconductor components is miniaturized to increase integration degree, then the integration degree is improved, but the parasitic capacitance becomes larger
Solution Approach 1:
The patent extracts and removes the polysilicon fill material from the trench structure. By taking out the polysilicon that was previously used to fill the trench space, the invention eliminates the source of parasitic capacitance while maintaining the trench's structural function for isolating adjacent semiconductor components
Solution Approach 2:
The patent applies different material properties to different regions: the trench is filled with a material having lower dielectric constant than polysilicon, and the trench depth is selectively controlled to expose the first oxide layer in specific regions. This local differentiation reduces parasitic capacitance in critical areas while maintaining component functionality
2Productivity
If the structure of semiconductor components is miniaturized, then the integration degree is improved, but the component volume reduction is insufficient
Solution Approach 1:
The patent utilizes the vertical dimension by controlling trench depth to expose the first oxide layer, creating a three-dimensional structure that optimizes space utilization. This dimensional approach allows for reduced component footprint while maintaining necessary isolation functions
Solution Approach 2:
The patent changes the dielectric parameter by replacing polysilicon fill with materials having lower dielectric constant, and adjusts the geometric parameter of trench depth to optimize the balance between isolation effectiveness and component volume reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance and volume of semiconductor components, enhancing their performance and integration.
Implementation Method 1
a first oxide layer is deposited on the array region
Implementation Method 2
a second polysilicon layer is deposited to cover the first oxide layer, the trench, the boundary open region
Implementation Method 3
a metal layer is deposited on the first oxide layer, a remaining portion of the second polysilicon layer
Implementation Method 4
a portion of the second oxide layer on the array region and the boundary open region and a portion of the first polysilicon layer on the array region and the boundary open region are removed
Data Source
AI summary
A semiconductor component includes a semiconductor substrate, a first oxide layer, an oxide, a first polysilicon layer, a first metal layer, a first mask on the first metal layer, and a bitline. The semiconductor substrate includes an array region, a periphery region and a boundary open region. The boundary open region isolates the array region from the periphery region. The first oxide layer is deposited on the array region. The first polysilicon layer is deposited on the periphery region. The first metal layer is deposited on the first polysilicon layer. A trench is formed on the array region and passes through the first oxide layer. The bitline includes a second polysilicon layer filling in the trench and a second metal layer on the second polysilicon layer. A second mask is formed on the second metal layer. The second polysilicon layer is flush with the first oxide layer.