Semiconductor System Patrol Training for Signal Delay Adjustment
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Solution Overview
Problem
As semiconductor devices operate at higher speeds, the increased input/output data rates lead to higher error probabilities during data transmission, necessitating additional methods to ensure data reliability, particularly in systems with varied memory circuit locations and signal transmission line lengths.
Innovation Solution
A semiconductor system that includes a process control circuit to determine and adjust delay amounts in signal transmission circuits coupling controllers and memory circuits, an operation control circuit to manage write and read operations, a scrub control circuit to generate scrub signals, and an error detection circuit to detect and correct errors, thereby performing patrol training operations to maintain data reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the input/output speed of data is increased to increase operating speed, then productivity is improved, but the probability of error during data transmission increases, worsening reliability
Solution Approach 1:
The patent performs patrol training operations before normal data transmission to pre-adjust delay amounts of delay cells. This preliminary calibration of signal timing ensures that high-speed data transmission can proceed with minimized errors, allowing the system to achieve high operating speed while maintaining reliability through advance preparation of the transmission path.
Solution Approach 2:
The error detection circuit monitors data transmission and generates fail information signals when errors occur. This feedback mechanism allows the system to detect transmission errors at high speeds and trigger appropriate corrective actions, enabling the system to maintain reliability even when operating at increased data rates.
2Device complexity
If memory circuits are placed at various locations to increase integration, then device complexity is reduced, but signal transmission line lengths vary, worsening manufacturing precision of signal timing
Solution Approach 1:
The patent applies local quality by individually adjusting the delay amounts of delay cells associated with each memory circuit based on their specific locations. The process control circuit determines optimal delay amounts for each memory circuit separately, compensating for variations in signal transmission line lengths caused by different physical locations, thus maintaining signal timing precision across the integrated system.
Solution Approach 2:
The patent makes the delay amount dynamic by allowing it to be adjusted based on the specific memory circuit being accessed. The delay cell can change its delay characteristic according to the patrol training results for different memory circuits, enabling the system to adapt to varying transmission line lengths and maintain precise signal timing despite memory circuits being placed at various locations.
Data Source
AI summary
A semiconductor system includes a process control circuit configured to determine whether to perform a patrol training operation, generate a voltage code signal for adjusting a level of a reference voltage which determines a logic level of data in a target memory circuit, and adjust the voltage code signal on the basis of a fail information signal corresponding to the target memory circuit, an operation control circuit configured to receive a command and an address from a host, generate, from the command, a write signal and a read signal for performing a normal operation, and generate, from the address, an internal address for performing the normal operation and an error detection circuit configured to detect an error in the data by receiving the data from the target memory circuit, and generate the fail information signal depending on whether the error has occurred in the data.