Semiconductor Pillar Formation for High-Density Memory
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Solution Overview
Problem
The integration density of transistors in memory devices is limited by the narrow-width and short-channel effects, which degrade transistor performance and restrict further increases in storage density.
Innovation Solution
A semiconductor structure is formed by providing a substrate with a sacrificial layer and an active layer, patterning to create grooves and isolation layers, removing the sacrificial layer to form gaps, and depositing bit lines and semiconductor pillars to enhance transistor density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the channel size of the transistor is decreased to increase storage density, then the storage density of the memory is increased, but the performance of the transistor is degraded due to narrow-width effect and short-channel effect
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional vertically-chained transistors (VCTs), stacking multiple transistor channels vertically along the channel direction. This dimensional change allows multiple channels to occupy the same footprint area, increasing storage density without further reducing individual channel dimensions, thereby avoiding narrow-width and short-channel effects while maintaining transistor performance.
2Productivity
If the channel size is reduced to increase integration density, then more transistors can be packed in the same area, but the narrow-width effect and short-channel effect cause performance degradation
Solution Approach 1:
The invention stacks multiple transistor channels vertically to form vertically-chained transistors, achieving higher integration density by utilizing the vertical dimension rather than further reducing horizontal channel dimensions. This approach maintains adequate channel size for each individual transistor, preventing narrow-width and short-channel effects while increasing the number of functional channels per unit area.
Solution Approach 2:
Multiple transistor channels are nested vertically within a single transistor structure, with channels stacked one above another along the vertical direction. This nesting arrangement allows multiple functional channels to be contained within a compact vertical space, achieving high integration density without compromising individual channel performance.
Data Source
AI summary
A semiconductor structure and a method for forming the same, and a memory and a method for forming the same are provided. The method for forming the semiconductor structure includes: providing a substrate, in which a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate; patterning the active layer and the sacrificial layer to form grooves which divide the active layer and the sacrificial layer into a plurality of active areas; filling the grooves to form a first isolation layer surrounding the active areas; patterning the active layer in the active areas to form a plurality of separate active patterns; removing the sacrificial layer via openings between adjacent active patterns to form gaps between bottoms of the active patterns and the substrate; forming bit lines in the gaps; and forming semiconductor pillars on partial tops of the active patterns.