Semiconductor Pin Cell EM Failure Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Electromigration (EM) effects in lower metal layers of integrated circuits become significant due to increasing current densities, leading to potential open-circuit failures and poor Power Performance Area (PPA) results, as traditional analysis focuses mainly on higher metal layers.
Innovation Solution
An EM-aware cell replacement technique is implemented during the synthesis and Automatic Placement and Routing (APR) flow, where each output pin of cells is assigned an appropriate output pin cell based on loading capacitance to alleviate EM phenomena and optimize pin density, using a library of output pin cells with varying capacitance capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional EM analysis focuses only on higher metal layers, then analysis complexity is reduced, but EM-induced failures in lower metal layers are not detected
Solution Approach 1:
The patent segments the EM analysis into two distinct parts: (1) traditional analysis of higher metal layers connecting cells, and (2) new analysis of lower metal layers within cells. This segmentation allows comprehensive EM detection across all metal layers while managing complexity by treating different layers with appropriate analysis methods.
Solution Approach 2:
The patent performs preliminary EM analysis on lower metal layers within cells during the placement and routing stages, before final design completion. This preliminary action identifies potential EM issues early, allowing designers to address them before fabrication, thereby improving reliability without adding significant complexity to the final analysis.
2Reliability
If BEOL resources are over-designed for cell EM signoff, then EM reliability is improved, but routing quality and PPA results deteriorate
Solution Approach 1:
The patent applies local quality by differentiating EM analysis and design rules for different metal layers. Lower metal layers within cells receive specific EM analysis and targeted design adjustments, while higher metal layers continue with traditional analysis. This localized approach ensures EM reliability where needed without over-designing entire cell structures, thus maintaining PPA performance.
Solution Approach 2:
The patent changes EM design parameters selectively based on metal layer and location. By adjusting EM signoff parameters only for lower metal layers within cells where current densities are highest, the patent achieves adequate EM protection without applying overly conservative parameters across all cells, thereby avoiding degradation of routing quality and PPA results.
Data Source
AI summary
A method of forming a semiconductor device including: providing a first circuit cell including a first pin cell; forming a connecting path originated from the first pin cell of the first circuit cell; performing an Electromigration (EM) checking process with a first parasitic capacitance of the first pin cell and a second parasitic capacitance of the connecting path by loading a loading capacitance file to determine whether the loading capacitance of the first pin cell is larger than a first predetermined capacitance; and substituting a second pin cell for the first pin cell when the loading capacitance of the first pin cell is larger than the first predetermined capacitance, wherein the second pin cell is different from the first pin cell.