Semiconductor Pin Pattern Optimization via Routing Feedback
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Solution Overview
Problem
The increasing demand for high-performance, low-power consumption semiconductor devices with high integration density poses challenges in designing and manufacturing semiconductor devices with efficient interconnections that balance complexity and reliability.
Innovation Solution
A method for designing and manufacturing semiconductor devices involves creating standard cell layouts with preliminary pin patterns, performing routing steps to generate high-level interconnection layouts, and adjusting pin patterns based on hitting information to optimize interconnections, resulting in smaller pin patterns that reduce parasitic capacitance and enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If preliminary pin patterns are designed with fixed size before routing, then routing can be performed systematically, but pin patterns cannot be optimized based on actual routing requirements leading to increased parasitic capacitance
Solution Approach 1:
The patent applies preliminary action by designing preliminary pin patterns with larger sizes before routing to ensure adequate routing flexibility, then subsequently adjusting them to smaller optimized sizes after routing completion. This two-stage approach allows the system to benefit from both adequate initial routing capability and final optimization for reduced parasitic capacitance.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the size parameter of pin patterns based on routing outcomes. The pin pattern size transitions from a larger preliminary dimension to a smaller final dimension, optimizing the balance between routing flexibility and parasitic capacitance reduction.
2Use of energy by moving object
If pin patterns are made smaller to reduce parasitic capacitance, then power consumption decreases, but routing flexibility is reduced making interconnection more difficult
Solution Approach 1:
The patent uses preliminary action by initially creating pin patterns with larger sizes that provide adequate routing flexibility, performing routing operations, and then reducing the pin pattern sizes to minimize parasitic capacitance and power consumption. This sequence ensures routing is not constrained while achieving energy efficiency.
Solution Approach 2:
The patent applies parameter changes by adjusting the size parameter of pin patterns from larger preliminary dimensions to smaller final dimensions. This dynamic parameter adjustment optimizes the trade-off between routing flexibility (requiring larger patterns) and power consumption (reduced with smaller patterns).
3Ease of manufacture
If standard cell layouts use uniform pin patterns, then manufacturing is simplified, but all cells cannot be optimized for their specific routing requirements
Solution Approach 1:
The patent implements preliminary action by establishing uniform preliminary pin patterns across all standard cells for simplified manufacturing and layout standardization. After routing is completed and hitting information is obtained, the pin patterns are then customized to specific sizes and configurations based on individual cell routing requirements, achieving both manufacturing ease and performance optimization.
Solution Approach 2:
The patent applies local quality by transitioning from uniform preliminary pin patterns to customized final pin patterns with different sizes and configurations tailored to specific cell requirements. This allows each standard cell to have optimized interconnection characteristics while maintaining overall manufacturing efficiency through the standardized preliminary design.
Data Source
AI summary
A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.