3D Semiconductor Pipe Transistor Vertical Plug Asymmetry
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Solution Overview
Problem
Three-dimensional semiconductor devices face challenges in achieving improved electrical characteristics in source and drain regions due to differences in electrical characteristics between these regions, which affect the performance and reliability of the devices.
Innovation Solution
A 3-D semiconductor device is designed with first and second vertical plugs of different sizes, connected to a pipe transistor, where the plugs are formed with varying widths to optimize program disturbances and operation speeds, and a manufacturing method involving alternately stacking sacrificial layers and interlayer insulating layers to create these plugs and improve electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertical plugs of the same size are used in source and drain regions, then the device structure is simple and manufacturing is easier, but electrical characteristics differ between source and drain regions leading to performance degradation
Solution Approach 1:
The patent applies local quality by forming first and second vertical plugs with different cross-sectional areas in the source and drain regions respectively. The first vertical plug has a first cross-sectional area while the second vertical plug has a second cross-sectional area that is different from the first. This allows each region to have optimized electrical characteristics tailored to its specific functional requirements, resolving the contradiction between uniform simple structure and differentiated performance.
Solution Approach 2:
The patent implements asymmetry by intentionally designing the vertical plugs to have unequal dimensions. Rather than using symmetric identical plugs in both source and drain regions, the structure employs asymmetric plug sizes to compensate for the inherently different electrical characteristics of source and drain regions, thereby improving overall device reliability while accepting increased structural complexity.
2Reliability
If larger vertical plugs are used to improve electrical connections, then electrical characteristics improve, but program disturbances increase and operation speed decreases
Solution Approach 1:
The patent applies local quality by forming first and second vertical plugs with different cross-sectional areas in the source and drain regions respectively. The first vertical plug has a first cross-sectional area while the second vertical plug has a second cross-sectional area that is different from the first. This allows each region to have optimized electrical characteristics tailored to its specific functional requirements, resolving the contradiction between uniform simple structure and differentiated performance.
Solution Approach 2:
The patent changes the physical parameters of the vertical plugs by varying their cross-sectional areas. By adjusting the size parameters of the plugs in different regions, the patent optimizes the balance between electrical connection quality and program operation characteristics, preventing both excessive program disturbances and maintaining adequate operation speed.
3Reliability
If different sized vertical plugs are used to optimize program disturbances and operation speeds, then electrical characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by forming a patterned mask layer before depositing the conductive material for the vertical plugs. This mask layer is prepared in advance with the specific pattern that defines the different cross-sectional areas of the first and second vertical plugs. By preparing the patterned mask beforehand, the subsequent deposition and formation processes become more straightforward, reducing the overall manufacturing complexity despite the differentiated plug structures.
Solution Approach 2:
The patent introduces a patterned mask layer as an intermediary element that facilitates the formation of vertical plugs with different cross-sectional areas. This mask layer acts as a mediator that defines the geometry and dimensions of the plugs during the deposition process, making it easier to achieve the desired asymmetric structure without requiring complex direct fabrication techniques.
Data Source
AI summary
There are provided a 3-D semiconductor device and a manufacturing method thereof. The 3-D semiconductor device includes a substrate extending along a first plane defined by first and second x and y directions, the substrate having a pipe transistor formed therein, a plurality of word lines spaced apart at regular intervals along a third direction z perpendicular to the first and second x and y directions; a first vertical plug connected to a first end of the pipe transistor by passing vertically through the word lines; a second vertical plug, connected to a second end of the pipe transistor by passing vertically through the word lines; a bit line connected to a top surface of the first vertical plug; and a source line connected to a top surface of the second vertical plug, wherein the first and second vertical plugs have different size.


