Semiconductor Plug Structure with Hard Mask Etch Stop
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Solution Overview
Problem
In semiconductor fabrication, the etching process for forming vertical connections can lead to over-etching of inter-dielectric layers, resulting in a 'tiger-tooth' structure at the edge of upper-level plugs, which compromises the quality of the semiconductor device.
Innovation Solution
A method involving the formation of a dishing in the first inter-dielectric layer, followed by a hard mask layer that serves as an etching stop, and subsequent formation of a second plug structure with an edge portion extending on the hard mask layer, effectively preventing over-etching and reducing the occurrence of tiger-tooth structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the etching process is used to form via openings in the inter-dielectric layer, then the vertical connection between levels is achieved, but the inter-dielectric layer at the lower level is over-etched, causing an indent structure (tiger-tooth) to form
Solution Approach 1:
A hard mask layer is introduced as an intermediary between the upper and lower inter-dielectric layers. This hard mask layer serves as an etching stop layer that prevents the etching process from damaging the lower inter-dielectric layer, thereby eliminating the tiger-tooth structure while still allowing via openings to be formed in the upper layer
Solution Approach 2:
The hard mask layer is formed in advance before the via opening etching process. By preparing this protective layer beforehand, the patent prevents over-etching from occurring during the subsequent etching step, thus avoiding the formation of harmful indent structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of semiconductor devices by minimizing the formation of tiger-tooth structures, ensuring precise and reliable vertical connections between different levels of the semiconductor device.
Implementation Method 1
performing a polishing process over the first inter-dielectric layer to have a dishing on top
Implementation Method 2
the hard mask layer serves as an etching stop layer, when the second inter-dielectric layer is patterned to have an opening to expose the first plug structure
Data Source
AI summary
A method for fabricating a semiconductor device is provided including providing a substrate, on which a plurality of elements is formed. A first inter-dielectric layer is formed over the substrate, covering the elements. A first plug structure is formed in the first inter-dielectric layer, including performing a polishing process over the first inter-dielectric layer to have a dishing on top and extending from a sidewall of the first plug structure. A hard mask layer is formed to fill the dishing. A second inter-dielectric layer is formed over the hard mask layer. A second plug structure is formed in the second inter-dielectric layer to electrically contact the first plug structure, wherein the second plug structure has at least an edge portion extending on the hard mask layer.