Semiconductor Device With Vertical Polysilicon Protection Circuits
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Solution Overview
Problem
Existing semiconductor devices face challenges in increasing chip size to accommodate additional zener diodes for improved electrostatic discharge resistance, leading to cost increases and reduced flexibility in chip design due to limited bonding pad areas.
Innovation Solution
The semiconductor device incorporates first and second protection circuits formed in separate polysilicon layers on a single field insulating film, allowing for wider gate pad arrangement and improved layout flexibility without increasing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional zener diodes are added to improve electrostatic discharge resistance, then protection capability is improved, but chip size increases
Solution Approach 1:
The patent utilizes vertical layering of polysilicon regions (first polysilicon layer and second polysilicon layer) to arrange protection circuits in the vertical dimension rather than expanding horizontally. This allows multiple zener diodes to be stacked vertically, improving electrostatic discharge protection capability while maintaining the same chip footprint area.
Solution Approach 2:
The patent implements nested arrangement where the first protection circuit and second protection circuit are positioned such that one is contained within or adjacent to the other in the vertical direction. The first polysilicon layer and second polysilicon layer are arranged in an overlapping or adjacent vertical configuration, allowing compact integration of multiple protection functions within a single vertical column space.
2Reliability
If dedicated area is allocated for zener diodes, then protection circuit functionality is improved, but bonding pad arrangement flexibility is reduced
Solution Approach 1:
By arranging protection circuits vertically in multiple polysilicon layers, the patent frees up horizontal bonding pad areas for flexible gate pad arrangement. The vertical stacking of protection circuits removes the constraint of dedicating horizontal bonding pad areas, allowing gate pads to be positioned optimally for electrical connection without interfering with zener diode placement.
3Area of stationary object
If clamp diodes are arranged inside zener diodes, then chip size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides protection circuits into separate first and second polysilicon layers, with each layer containing distinct zener diodes. This segmentation into discrete vertical layers simplifies manufacturing by allowing independent formation and patterning of each protection circuit layer, avoiding the complexity of integrating clamp diodes within the same planar space as zener diodes.
Data Source
AI summary
A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film.