Semiconductor Die Coupling With U-Shaped RDL Daisy Chains
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Solution Overview
Problem
Three-dimensional (3D) memory devices face signal integrity degradation and increased power consumption due to the heavy load presented by stacked dies, which can lead to improper data latching and unacceptable performance in certain applications.
Innovation Solution
The use of a daisy chain coupling method through conductive structures, specifically a redistribution layer (RDL) with a 'U' shape, to connect terminals of semiconductor devices to bond pads, reducing the load on the circuit and improving signal integrity by distributing the electrical load serially rather than in parallel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked dies are coupled in parallel to external circuit, then memory capacity and bandwidth are increased, but signal integrity degrades and power consumption increases due to heavy load
Solution Approach 1:
The patent segments the parallel coupling architecture into a daisy-chain serial coupling architecture. Instead of connecting all stacked dies in parallel to the external circuit, the dies are connected sequentially in a daisy-chain manner, where each die couples to the next die in sequence. This segmentation of the coupling topology transforms the heavy parallel load into distributed serial connections, reducing the signal integrity degradation and power consumption while maintaining the memory capacity and bandwidth improvements.
2Quantity of substance
If stacked dies are coupled in parallel to external circuit, then memory capacity is increased, but power consumption increases due to heavy load
Solution Approach 1:
The patent applies segmentation by dividing the parallel power distribution network into a daisy-chain serial power distribution network. Each die in the stack receives power through sequential coupling rather than simultaneous parallel connection, which reduces the instantaneous power demand on the external circuit and improves overall power efficiency while maintaining the increased memory capacity provided by the stacked architecture.
3Productivity
If stacked dies are coupled in parallel to external circuit, then bandwidth is increased, but load on external circuit becomes heavy
Solution Approach 1:
The patent inverts the conventional parallel coupling approach by implementing daisy-chain serial coupling. Instead of having the external circuit drive signals against the combined load of all stacked dies simultaneously, the signal path is inverted to flow sequentially through each die in the stack. This inversion of the coupling topology reduces the instantaneous load on the external circuit while maintaining the high bandwidth capability of the stacked memory architecture.
Data Source
AI summary
Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a “U” shape in some embodiments of the disclosure. Each end of the “U” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.